1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL ECE 448 Lecture 10 Memories: RAM, ROM

2. 2ECE 448 – FPGA and ASIC Design with VHDL Memory Types

3. 3ECE 448 – FPGA and ASIC Design with VHDL Memory Types Memory RAMROM Single portDual port With asynchronous read With synchronous read Memory

4. 4ECE 448 – FPGA and ASIC Design with VHDL FPGA Distributed Memory

5. 5ECE 448 – FPGA and ASIC Design with VHDL COUT D Q CK S R EC D Q CK R EC O G4 G3 G2 G1 Look-Up Table Carry & Control Logic O YB Y F4 F3 F2 F1 XB X Look-Up Table F5IN BY SR S Carry & Control Logic CIN CLK CE SLICE CLB Slice

6. 6ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx Multipurpose LUT

7. 7ECE 448 – FPGA and ASIC Design with VHDL RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X2S O1 D0 WE WCLK A0 A1 A2 A3 D1 O0 = = LUT or LUT RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 or Distributed RAM CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual- Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read

8. George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Block RAM (BRAM)

9. 9ECE 448 – FPGA and ASIC Design with VHDL RAM Blocks in Xilinx FPGAs The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

10. 10ECE 448 – FPGA and ASIC Design with VHDL Block RAM Spartan-3 Dual-Port Block RAM Port A Port B Block RAMs in Xilinx Spartan 3 FPGAs Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements 4 to 104 memory blocks 18 kbits = 18,432 bits per block (16 k without parity bits) Use multiple blocks for larger memories Can be used to build both single-port and true dual-port RAMs

11. 11ECE 448 – FPGA and ASIC Design with VHDL Spartan-3 Block RAM Amounts

12. 12ECE 448 – FPGA and ASIC Design with VHDL Block RAM Port Aspect Ratios 0 16,383 1 4,095 4 0 8,191 2 0 2047 8+1 0 1023 16+2 0 16k x 1 8k x 2 4k x 4 2k x (8+1) 1024 x (16+2)

13. 13ECE 448 – FPGA and ASIC Design with VHDL Block RAM Port Aspect Ratios

14. 14ECE 448 – FPGA and ASIC Design with VHDL Single-Port Block RAM

15. 15ECE 448 – FPGA and ASIC Design with VHDL Dual-Port Block RAM

16. 16ECE 448 – FPGA and ASIC Design with VHDL RAMB4_S16_S8 Port A Out 18-Bit Width Port B In 2k-Bit Depth Port A In 1K-Bit Depth Port B Out 9-Bit Width DOA[17:0] DOB[8:0] WEA ENA RSTA ADDRA[9:0] CLKA DIA[17:0] WEB ENB RSTB ADDRB[10:0] CLKB DIB[8:0] Dual-Port Bus Flexibility Each port can be configured with a different data bus width Provides easy data width conversion without any additional logic

17. 17ECE 448 – FPGA and ASIC Design with VHDL 0, ADDR[12:0] 1, ADDR[12:0] RAMB4_S1_S1 Port B Out 1-Bit Width DOA[0] DOB[0] WEA ENA RSTA ADDRA[12:0] CLKA DIA[0] WEB ENB RSTB ADDRB[12:0] CLKB DIB[0] Port B In 8K-Bit Depth Port A Out 1-Bit Width Port A In 8K-Bit Depth Two Independent Single-Port RAMs To access the lower RAM Tie the MSB address bit to Logic Low To access the upper RAM Tie the MSB address bit to Logic High Added advantage of True Dual- Port No wasted RAM Bits Can split a Dual-Port 16K RAM into two Single-Port 8K RAM Simultaneous independent access to each RAM

18. 18ECE 448 – FPGA and ASIC Design with VHDL Inference vs. Instantiation

19. 19ECE 448 – FPGA and ASIC Design with VHDL

20. 20ECE 448 – FPGA and ASIC Design with VHDL

21. 21ECE 448 – FPGA and ASIC Design with VHDL Generic Inferred Memories

22. 22ECE 448 – FPGA and ASIC Design with VHDL Generic RAM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY ram IS GENERIC (bits: INTEGER :=8; -- # of bits per word words: INTEGER := 256); -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0); wr_ena: IN STD_LOGIC; clk: IN STD_LOGIC; data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) ); END ram;

23. 23ECE 448 – FPGA and ASIC Design with VHDL Single-port RAM with asynchronous read (2) ARCHITECTURE async_read_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN data_out <= memory(addr); PROCESS(clk) BEGIN IF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THEN memory(addr) <= data_in; END IF; END PROCESS; END async_read_RAM;

24. 24ECE 448 – FPGA and ASIC Design with VHDL Report from Synthesis (1) Mapping to part: xc3s50vq100-5 Cell usage: MUXF5 8 uses RAM64X1S 32 uses LUT3 20 uses RAM/ROM usage summary Single Port Rams (RAM64X1S): 32 Mapping Summary: Total LUTs: 148 (9%)

25. 25ECE 448 – FPGA and ASIC Design with VHDL Report from Implementation (1) Target Device : xc3s50 Target Package : vq100 Target Speed : -5 Design Summary -------------- Logic Utilization: Number of 4 input LUTs: 20 out of 1,536 1% Logic Distribution: Number of occupied Slices: 74 out of 768 9% Number of Slices containing only related logic: 74 out of 74 100% Number of Slices containing unrelated logic: 0 out of 74 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 148 out of 1,536 9% Number used as logic: 20 Number used for 32x1 RAMs: 128 (Two LUTs used per 32x1 RAM)

26. 26ECE 448 – FPGA and ASIC Design with VHDL ARCHITECTURE sync_read_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS(clk) BEGIN IF (rising_edge(clk)) THEN IF(wr_ena=‘1’) THEN memory(addr) <= data_in; ELSE data_out <= memory(addr); END IF; END PROCESS; END sync_read_RAM; Single-port RAM with synchronous read (2)

27. 27ECE 448 – FPGA and ASIC Design with VHDL Report from Synthesis (2) Mapping to part: xc3s50pq208-5 Cell usage: GND 1 use RAMB16_S9 1 use VCC 1 use RAM/ROM usage summary Block Rams : 1 of 4 (25%) Mapping Summary: Total LUTs: 0 (0%)

28. 28ECE 448 – FPGA and ASIC Design with VHDL Report from Implementation (2) Target Device : xc3s50 Target Package : pq208 Target Speed : -5 Design Summary -------------- Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 26 out of 124 20% Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12%

29. 29ECE 448 – FPGA and ASIC Design with VHDL Generic ROM (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------- ENTITY rom IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 TO words-1; data_out: OUT STD_LOGIC_VECTOR(bits – 1 DOWNTO 0) ); END rom;

30. 30ECE 448 – FPGA and ASIC Design with VHDL Generic ROM (2) ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000"); BEGIN data_out <= memory(addr); END rom;

31. 31ECE 448 – FPGA and ASIC Design with VHDL Generic ROM (3) – hexadecimal notation ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80"); BEGIN data_out <= memory(addr); END rom;

32. 32ECE 448 – FPGA and ASIC Design with VHDL std_logic vs. std_ulogic TYPE std_ulogic IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); SUBTYPE std_logic IS std_ulogic RANGE ‘X’ TO ‘-’;

33. 33ECE 448 – FPGA and ASIC Design with VHDL Conversion std_logic_vector => integer (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL u_addr: UNSIGNED(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= unsigned(stdl_addr); i_addr <= conv_integer(u_addr); end behavior;

34. 34ECE 448 – FPGA and ASIC Design with VHDL Conversion std_logic_vector => integer (2) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i_addr : INTEGER; begin u_addr <= conv_integer(unsigned(stdl_addr)); end behavior;

35. 35ECE 448 – FPGA and ASIC Design with VHDL Instruction ROM example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY instruction_rom IS GENERIC ( w : INTEGER := 16; n : INTEGER := 8; m : INTEGER := 3); PORT ( Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0); Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0) ); END instruction_rom;

36. 36ECE 448 – FPGA and ASIC Design with VHDL Instruction ROM example (2) ARCHITECTURE ins_rom OF insstruction_rom IS SIGNAL temp: INTEGER RANGE 0 TO 7; TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0); CONSTANT memory : vector_array := ("0000_0000_0000_0000", "0000_0000_0000_0000", "1101_0100_0101_1001", "1101_0100_0101_1000", "0110_1000_1000_0111", "0100_1001_1001_1010", "1111_0110_0111_0101", "1111_0110_0111_0100", BEGIN temp <= conv_integer(unsigned(Instr_addr)); Instr <= memory(temp); END instruction_rom;

37. 37ECE 448 – FPGA and ASIC Design with VHDL Generic dual-port memory with asynchronous output (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY dual_port_RAM IS PORT( wen : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); addr1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); addr2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); data_out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END dual_port_RAM;

38. 38ECE 448 – FPGA and ASIC Design with VHDL Generic dual-port memory with asynchronous output (2) ARCHITECTURE async_read_RAM OF dual_port_RAM IS TYPE vector_array IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL memory : vector_array; SIGNAL temp1: INTEGER RANGE 0 TO 31; SIGNAL temp2: INTEGER RANGE 0 TO 31; BEGIN temp1 <= conv_integer(unsigned(addr1)); temp2 <= conv_integer(unsigned(addr2)); data_out1 <= memory(temp1); data_out2 <= memory(temp2); PROCESS(clk) BEGIN IF (rising_edge(clk)) THEN IF (wen = '1') THEN memory(temp2) <= data_in; END IF; END PROCESS; END async_read_RAM;

39. 39ECE 448 – FPGA and ASIC Design with VHDL Report from Implementation Target Device : xc3s50 Target Package : pq208 Target Speed : -5 Design Summary -------------- Logic Utilization: Number of 4 input LUTs: 66 out of 1,536 4% Logic Distribution: Number of occupied Slices: 97 out of 768 12% Number of Slices containing only related logic: 97 out of 97 100% Number of Slices containing unrelated logic: 0 out of 97 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 194 out of 1,536 12% Number used as logic: 66 Number used for Dual Port RAMs: 128 (Two LUTs used per Dual Port RAM)

40. 40ECE 448 – FPGA and ASIC Design with VHDL attribute syn_ramstyle : string; attribute syn_ramstyle of memory : signal is "block_ram"; Specification of memory types recognized by Synplify Pro attribute syn_ramstyle : string; attribute syn_ramstyle of memory : signal is “select_ram"; LUT-based Distributed Memory: Block RAM Memory: SIGNAL memory : vector_array;

41. 41ECE 448 – FPGA and ASIC Design with VHDL FPGA specific memories

42. 42ECE 448 – FPGA and ASIC Design with VHDL RAM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC ); end RAM_16X1_DISTRIBUTED;

43. 43ECE 448 – FPGA and ASIC Design with VHDL RAM 16x1 (2) architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of RAM_16x1s_1: label is "0000"; ------------------------------------------------------------------------ component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component;

44. 44ECE 448 – FPGA and ASIC Design with VHDL RAM 16x1 (3) begin RAM_16x1s_1: ram16x1s generic map (INIT => X”0000") port map (O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE ); end RAM_16X1_DISTRIBUTED_STRUCTURAL;

45. 45ECE 448 – FPGA and ASIC Design with VHDL RAM 16x8 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity RAM_16X8_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0) ); end RAM_16X8_DISTRIBUTED;

46. 46ECE 448 – FPGA and ASIC Design with VHDL RAM 16x8 (2) -- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of RAM_16x1_S_1: label is "0000"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component;

47. 47ECE 448 – FPGA and ASIC Design with VHDL RAM 16x8 (3) begin GENERATE_MEMORY: for I in 0 to 7 generate RAM_16x1_S_1: ram16x1s generic map (INIT => X"0000") port map (O => DATA_OUT(I), A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN(I), WCLK => CLK, WE => WE ); end generate; end RAM_16X8_DISTRIBUTED_STRUCTURAL;

48. 48ECE 448 – FPGA and ASIC Design with VHDL ROM 16x1 (1) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT : out STD_LOGIC ); end ROM_16X1_DISTRIBUTED;

49. 49ECE 448 – FPGA and ASIC Design with VHDL ROM 16x1 (2) architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is -- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of rom16x1s_1: label is "F0C1"; component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000"); port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic); end component; signal Low : std_ulogic := ‘0’;

50. 50ECE 448 – FPGA and ASIC Design with VHDL ROM 16x1 (3) begin rom16x1s_1: ram16x1s generic map (INIT => X"F0C1") port map (O=>DATA_OUT, A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low ); end ROM_16X1_DISTRIBUTED_STRUCTURAL;

51. 51ECE 448 – FPGA and ASIC Design with VHDL ComponentData CellsParity CellsAddress BusData BusParity Bus DepthWidthDepthWidth RAMB16_S1163841--(13:0)(0:0)- RAMB16_S281922--(12:0)(1:0)- RAMB16_S440964--(11:0)(3:0)- RAMB16_S920488 1(10:0)(7:0)(0:0) RAMB16_S1810241610242(9:0)(15:0)(1:0) RAMB16_S36512325124(8:0)(31:0)(3:0) Block RAM library components

52. 52ECE 448 – FPGA and ASIC Design with VHDL Component declaration for BRAM (1) -- Component Declaration for RAMB16_{S1 | S2 | S4} -- Should be placed after architecture statement but before begin keyword component RAMB16_{S1 | S2 | S4} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; ………………………………… INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0) ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;

53. 53ECE 448 – FPGA and ASIC Design with VHDL Genaral template of BRAM instantiation (1) -- Component Attribute Specification for RAMB16_{S1 | S2 | S4} -- Should be placed after architecture declaration but before the begin keyword -- Put attributes, if necessary -- Component Instantiation for RAMB16_{S1 | S2 | S4} -- Should be placed in architecture after the begin keyword RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value, INIT_01 => vector_value, …………………………….. INIT_3F => vector_value, SRVAL=> bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, EN => user_EN, SSR => user_SSR, WE => user_WE);

54. 54ECE 448 – FPGA and ASIC Design with VHDL INIT_00 : BIT_VECTOR := X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040"; INIT_01 : BIT_VECTOR := X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026"; INIT_02 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000"; …………………………………………………………………………………………………………………………………… INIT_0F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000") 0000 F0 0000 F1 0000 F2 0000 F3 0000 F4 0000 FE 0000 FF INIT_0F ADDRESS 0026 10 0917 11 03AA 12 0C0F 13 014A 14 0000 1E 0000 1F INIT_01 ADDRESS 0040 00 0006 01 0068 02 006A 03 0917 04 0C0F 0E 014A 0F INIT_00 ADDRESS Addresses are shown in red and data corresponding to the same memory location is shown in black ADDRESS DATA Initializing Block RAMs 256x16

55. 55ECE 448 – FPGA and ASIC Design with VHDL Component declaration for BRAM (2) VHDL Instantiation Template for RAMB16_S9, S18 and S36 -- Component Declaration for RAMB16_{S9 | S18 | S36} component RAMB16_{S9 | S18 | S36} -- synthesis translate_off generic ( INIT : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL : bit_vector := X"0"; WRITE_MODE : string := "WRITE_FIRST"; ); -- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); DOP : out STD_LOGIC_VECTOR (1 downto 0); ADDR : in STD_LOGIC_VECTOR (13 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; SSR : in STD_ULOGIC; WE : in STD_ULOGIC); end component;

56. 56ECE 448 – FPGA and ASIC Design with VHDL -- Component Attribute Specification for RAMB16_{S9 | S18 | S36} -- Component Instantiation for RAMB16_{S9 | S18 | S36} -- Should be placed in architecture after the begin keyword RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1 -- synthesis translate_off generic map ( INIT => bit_value, INIT_00 => vector_value,.......... INIT_3F => vector_value, INITP_00 => vector_value, …………… INITP_07 => vector_value SRVAL => bit_value, WRITE_MODE => user_WRITE_MODE) -- synopsys translate_on port map (DO => user_DO, DOP => user_DOP, ADDR => user_ADDR, CLK => user_CLK, DI => user_DI, DIP => user_DIP, EN => user_EN, SSR => user_SSR, WE => user_WE); Genaral template of BRAM instantiation (2)

57. 57ECE 448 – FPGA and ASIC Design with VHDL Block RAM Waveforms – WRITE_FIRST

58. 58ECE 448 – FPGA and ASIC Design with VHDL Block RAM Waveforms – READ_FIRST

59. 59ECE 448 – FPGA and ASIC Design with VHDL Block RAM Waveforms – NO_CHANGE