1. REGISTER MANAGMENT TOOL Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 29/1/2012 winter semester 2011 Duration: One semester Middle presentation

2. Dress Specifications:  Color: White  Fabric: Lace  Length: Long Different designer - Different dress ! Motivation:

3. Background Different teams use the register HSID But each team creates their own registers code… WHY?!?

4. Automatically generates registers according to the required specification. The Solution – a Register Management Tool Creates unity in the registers VHD files Enables REUSE Saves money and resources

5. Manages the registers through the entire project Creates documentation for the components created Leads to an organized – HSID The Solution – a Register Management Tool Alarms in case of incorrect input

6. Project Specifications 1. Writing a GUI interface through which the user will determine a variety of attributes. GUI demo

7. Project Specifications 1. Writing a GUI interface through which the user will determine a variety of attributes. GUI demo 2. Interactivity - The tool will provide feedback for user errors end will provide a summary output.

8. Project Specifications 1. Writing a GUI interface through which the user will determine a variety of attributes. 3. VHDL: VHD files 1 Local Bus Master 2 Simulation Environment 3 2. Interactivity - The tool will provide feedback for user errors end will provide a summary output. GUI demo

9. Project Specifications 1. Writing a GUI interface through which the user will determine a variety of attributes. 4. No special license will be needed to operate the tool, an EXE file will be given to the user. 3. VHDL: VHD files 1 Local Bus Master 2 Simulation Environment 3 2. Interactivity - The tool will provide feedback for user errors end will provide a summary output. GUI demo

10. General Description Block Local Bus Chip data I/O Register access Register Block

11. Wishbone - open source protocol Block C Block A Wishbone Master clk_i cyc_i stb_i adr_i dat_i dat_o ack_o Stall_o we_i Block B

12. Top Architecture Block_A_reg_top Function_2 Function_3 Function_1 Block A Reg_status_1 Wishbone Master Reg_enable_2 func_err_3 resetclk

13. Reg Block Architecture WB Slave Reg1 Reg2 Reg3 Reg4 Priority Encoder reg_chosen 4 WB Master Functional Block Data from chosen register Inputs from block Outputs to block Block_A_reg_top

14. Wishbone Slave Component WB Slave clk_i wbs_cyc_i wbs_stb_i wbs_we_i wbs_adr_i wbs_dat_i wbs_dat_o wbs_stall_o wbs_ack_o dout din_ack dout_valid rd_en din addr wr_en

15. Wishbone Slave Component Idle wr_en=‘0’ rd_en=‘0’ Read Cycle rd_en=‘1’ (wbs_cyc_i ) ● (wbs_stb_i) Active Cycle wbs_stall_o=‘1’ Write Cycle wr_en=‘1’ wbs_we_i Cycle Finished wbs_ack_o=‘1’ dout_valid din_ack wbs_cyc_i

16. gen_reg Component addr din wr_en rd_en dout din_ack reg_chosen dout_valid gen_reg clk reset reg_in_b

17. Idle reg_chosen=‘0’ din_ack=‘0’ dout_valid=‘0’ Read action addr==reg addr The Register is chosen reg_chosen=‘1’ Write action addr==reg addr rd_en wr_en addr==reg addr gen_reg Component Invalid Read Action dout_valid=‘0’ Valid Read Action dout_valid=‘1’ Valid Write Action din_ack=‘1’ Invalid write Action din_ack=‘0’ Register type is W Register type is R/RW/COR/CONST Register type is W/RW Register type is R/COR/CONST

18. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block

19. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block

20. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block

21. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block “0000”

22. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block “0100”

23. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block “0001” “0101”

24. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block rd_en = ‘1’ “0000” “0101”

25. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block “0000” “1010” “0000”

26. Register Types Read Write W/R Clear on Read (COR) Constant register Wishbone Master Functional Block Reg Block

27. Generic Implementation

30. Simulation

31. COR register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ “00000000”

32. COR register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ “00010000”

33. COR register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ adr_i = 0010 we_i =‘0’ “00000000” “00010000”

34. COR register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ adr_i = 0010 we_i =‘0’ “00000000” dout =“00010000” dout_valid = ‘1’ din_ack = ‘0’

35. COR register waveform 0 Scenario: the block updates the data while the master reads rd_en =‘1’ Data from block = 1

36. COR register waveform Results: 0 dout = “1” Dout_valid = ‘1’ updated data is transferred to the WB master reg_data is cleared

37. COR register waveform 0 Reg_data = “00000000” Results: updated data is transferred to the WB master reg_data is cleared

38. W/R register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ “00000000” adr_i = 1110 we_i =‘1’ dat_i = “00001101” “00001101”

39. W/R register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ adr_i = 1110 we_i =‘0’ “00001101”

40. W/R register simulation WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master Functional Block........ dout =“00001101” dout_valid = ‘1’ din_ack = ‘0’ adr_i = 1110 we_i =‘0’

41. W/R register waveform Scenario: WB master writes to register din = 7 and then 8 wr_en = ‘1’ for 2 cycles

42. W/R register waveform dout = 7 and then 8 din_ack = ‘1’ for 2 cycles Results: updated data from WB master is transferred to register din_ack rises, indicating dout is updated Register not influenced by data from block (reg_in_b)

43. W/R register waveform Scenario: WB master tries to read from this register’s address (register address is 10) Result: dout_valid rises to ‘1’ Dout_valid = ‘1’ rd_en = ‘1’ addr = 10

44. W/R register waveform Scenario: WB master tries to read from another register’s address (register address is 10) Result: dout_valid is ‘0’ Dout_valid = ‘0’ rd_en = ‘1’ addr = 15

45. Project Steps 1.Determine the implementation platform of the user interface and data processing: Excel/MATLAB/C++/C#/JAVA. 2. Full characterization of the tool capabilities. 3. Learning the working environment (Wishbone protocol, advanced VHDL coding, MODELSIM simulation environment). 4.VHDL generic design and simulation. 5.Implementing the GUI and automatic VHDL generation. 6. Final MODELSIM and MATLAB Simulations. In process

46. Schedule

47. The End

48. GUI Demonstration Back