1. Host Port Interface Expansion Bus Chapter 16 C6000 Integration Workshop Copyright © 2005 Texas Instruments. All rights reserved. T TO Technical Training Organization

2. Objectives  HPI Overview  HPI on the DSK  Host Software Example  HPI Hardware Description  Optional Discussions T TO Technical Training Organization

3. Why HPI? CC CC ‘C6x Ser. Port 32 || Bus Ded. Bus Dedicated to memory accessDedicated to Codecs and A/D’s T TO Technical Training Organization

4. Why HPI for Communication?  Give host control of the transfer  Allow host to access the entire C6000 memory map  Additional parallel bus for data exchange between a host and the C6000  Provide glueless interface to many different types of hosts T TO Technical Training Organization

5. What are the requirements of the dedicated bus? Why HPI? CC CC ‘C6x Ser. Port 32 || Bus Ded. Bus Dedicated to memory accessDedicated to Codecs and A/D’s T TO Technical Training Organization

6. What are the requirements for the dedicated bus? 1. Address 2. Data 3. Control What are the requirements for the dedicated bus? 1. Address 2. Data 3. Control HPI Bus HPI Overview CC CC ‘C6x HPI HPIC HPIA HPID DMA Aux. Ch. Addr. Data Memory...... T TO Technical Training Organization

7. HPI Bus HPI Overview Since the HPI bus (HD) is only 16 bits wide, each read/write requires two operations. Since the HPI bus (HD) is only 16 bits wide, each read/write requires two operations. CC CC ‘C6x HPI HPIC HPIA HPID DMA Aux. Ch. Addr. Data Memory...... 16 T TO Technical Training Organization

8. Objectives HPI Overview  HPI on the DSK  Host Software Example  HPI Hardware Description  Optional Discussions T TO Technical Training Organization

9. Host  DSK Communications  The C6713 DSK has a HPI connector which brings out the pins of the Host Port Interface  On the C6416 DSK, this connector contains the muxed HPI/PCI pins  Also shown, the JTAG emulation connections DSP JTAG Emulation Port HPI connector USBUSB....... JTAG....... T TO Technical Training Organization

10. Objectives HPI Overview HPI on the DSK  Host Software Example  HPI Hardware Description  Optional Discussions T TO Technical Training Organization

11. Some Ideas for Host Interface API C6X_open( ) Open a connection to the C6000 C6X_close( ) Close a connection to the C6000 C6X_resetBoard( ) Reset the entire board C6X_resetDsp( ) Reset only the DSP on the board C6X_dspImageLoad( ) Load a DSP image (COFF) to DSP memory C6X_memRead( ) Read DSP memory via the HPI C6X_memWrite( ) Write to DSP memory via the HPI C6X_ctrlRead( ) Read HPI control register C6X_ctrlWrite( ) Write to HPI control register C6X_generateInt( ) Generate a DSP interrupt C6X_isr( ) Respond to host interrupt (HINT) from DSP  Here are some ideas for the host software (and hardware) functionality you might want to build into your system  These routines could be combined to create more advanced host functions (like routines for setting up the EDMA and such)  Unfortunately, we cannot provide these functions for you, as they must be written specific to the hardware of your host T TO Technical Training Organization

12. Objectives HPI Overview HPI on the DSK Host Software Example  HPI Hardware Description  Setup Control and Address  Writing 32-bits  Reading 32-bits  Sequential Accesses  Optional Discussions T TO Technical Training Organization

13. HPI Control Register 32-bit transfer = Minimum of 8 CPU cycles CC CC ‘C6x HPI HPIC HPIA HPID DMA Aux. Ch. Addr. Data Memory...... HD 16 T TO Technical Training Organization

14. Setup HPI Control Register HWOB 0 - Big Endian 1 - Little Endian HWOB 0 - Big Endian 1 - Little Endian HWOB reserved 015 5 HWOB reserved 1631 21  Setup the HPI Control register ( HWOB-bit ) to specify which 16-bits (upper or lower) are transferred first.  Similar to little/big endian.  Order doesn’t matter when writing to HPIC as the fields are aliased to both halves. T TO Technical Training Organization

15. Setup HPIC 1. Use HCNTL[1:0] = 00 b to enable access to HPIC CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data 2 HCNTL HPID HPIA Memory...... HD 16 HPIC HCNTL Values HCNTL1 HCNTL0Description 00HPIC 01HPIA 10HPID (HPIA++) 11HPID T TO Technical Training Organization

16. Setup HPIC CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data 2 HCNTL HPID HPIA Memory...... HD 16 HPIC HR/ W 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB= xxx1) 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB= xxx1) T TO Technical Training Organization

17. Setup HPIC - 1 CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HD 16 HPIC HR/ W HHWIL 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0), HD = ctrl bits (HWOB = xxx1) HHWIL = 0 indicates first halfword transfer 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0), HD = ctrl bits (HWOB = xxx1) HHWIL = 0 indicates first halfword transfer 2 HCNTL T TO Technical Training Organization

18. HSTRB - 2 CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC HSTRB 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 0 indicates first halfword transfer 2. HSTRB to indicate active 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 0 indicates first halfword transfer 2. HSTRB to indicate active HD 16 HR/ W HHWIL 2 HCNTL xxx1 T TO Technical Training Organization

19. Setup HPIC - 3 CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC 3. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 1 indicates second halfword transfer 3. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 1 indicates second halfword transfer HD 16 HR/ W HHWIL 2 HCNTL xxx1 T TO Technical Training Organization

20. Setup HPIC - 4 CC CC ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC HSTRB 3. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 1 indicates second halfword transfer 4. HSTRB to indicate active 3. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = xxx1) HHWIL = 1 indicates second halfword transfer 4. HSTRB to indicate active HD 16 HR/ W HHWIL 2 HCNTL xxx1 T TO Technical Training Organization

21. Setup HPIA - 1  C Write 8000_0000 to HPIA  C Write 8000_0000 to HPIA ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC 1. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0), HD = 0000 HHWIL = 0 indicates first halfword transfer 1. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0), HD = 0000 HHWIL = 0 indicates first halfword transfer HR/ W HHWIL HD 16 2 HCNTL xxx1 T TO Technical Training Organization

22. Setup HPIA - 2  C Write 8000_0000 to HPIA  C Write 8000_0000 to HPIA ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC HSTRB 1. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 0000 HHWIL = 0 indicates first halfword transfer 2. HSTRB to indicate active 1. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 0000 HHWIL = 0 indicates first halfword transfer 2. HSTRB to indicate active HD 16 HR/ W HHWIL 2 HCNTL xxx1 0000 T TO Technical Training Organization

23. Setup HPIA - 3  C Write 8000_0000 to HPIA  C Write 8000_0000 to HPIA ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC 3. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 8000 HHWIL = 1 indicates second halfword transfer 3. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 8000 HHWIL = 1 indicates second halfword transfer HD 16 HR/ W HHWIL 2 HCNTL xxx1 0000 T TO Technical Training Organization

24. Setup HPIA - 4  C Write 8000_0000 to HPIA  C Write 8000_0000 to HPIA ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC HSTRB 3. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 8000 HHWIL = 1 indicates second halfword transfer 4. HSTRB to indicate active 3. Use HCNTL[1:0] = 01 b to enable access to HPIA HR/ W to write (0). HD = 8000 HHWIL = 1 indicates second halfword transfer 4. HSTRB to indicate active HD 16 HR/ W HHWIL 2 HCNTL xxx1 00008000 T TO Technical Training Organization

25. Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Setup Control and Address  Writing 32-bits  Reading 32-bits  Sequential Accesses  Optional Discussions T TO Technical Training Organization

26. Example 1: Writing a 32-bit Value - 1 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 0, HD = 5678 HHWIL = 0 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 0, HD = 5678 HHWIL = 0  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HR/ W HPIC xxx1 T TO Technical Training Organization

27. Example 1: Writing a 32-bit Value - 2  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID 5678 DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HSTRB HR/ W HPIC xxx1 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 0, HD = 5678 HHWIL = 0 2. HSTRB 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 0, HD = 5678 HHWIL = 0 2. HSTRB T TO Technical Training Organization

28. Example 1: Writing a 32-bit Value - 3 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID 5678 DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HR/ W HPIC xxx1 T TO Technical Training Organization

29. Example 1: Writing a 32-bit Value - 4 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID 12345678 DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HR/ W HPIC xxx1 HSTRB T TO Technical Training Organization

30. Example 1: Writing a 32-bit Value - 5 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB 5. HRDY high (not-ready) until DMA is finished 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB 5. HRDY high (not-ready) until DMA is finished  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID 12345678 DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HSTRB HRDY  HPIC 8000 0000 1234 5678 xxx1 HR/ W T TO Technical Training Organization

31. Example 1: Writing a 32-bit Value - 5 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB 5. HRDY high (not-ready) until DMA is finished 3. HCNTL[1:0] = 11 b (HPID) HR/ W = 0 Write value: HHWIL = 1, HD = 1234 4. HSTRB 5. HRDY high (not-ready) until DMA is finished  C Write 1234_5678 to 8000_0000  C Write 1234_5678 to 8000_0000 ‘C6x HPI HPID 12345678 DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HD 16 HSTRB HPIC 8000 0000 1234 5678 xxx1 HR/ W T TO Technical Training Organization

32. Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Setup Control and Address Writing 32-bits  Reading 32-bits  Sequential Accesses  Optional Discussions T TO Technical Training Organization

33. Example 2: Reading a 32-bit Value - 1 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HR/ W HPIC 1234 5678 xxx1 T TO Technical Training Organization

34. Example 2: Reading a 32-bit Value - 2 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HSTRB HPIC 1234 5678 xxx1 HR/ W T TO Technical Training Organization

35. Example 2: Reading a 32-bit Value - 3 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address 3. HRDY is asserted until HD = 5678 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address 3. HRDY is asserted until HD = 5678  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 1234 5678 xxx1 HD 16 12345678 HR/ W HSTRB HRDY  1234 5678 5678 Host Data 8000 0000 T TO Technical Training Organization

36. Example 2: Reading a 32-bit Value - 3 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address 3. HRDY is asserted until HD = 5678 1. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB, HPIA is copied to DMA address 3. HRDY is asserted until HD = 5678  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 1234 5678 xxx1 HD 16 12345678 HR/ W HSTRB 1234 5678 5678 Host Data 8000 0000 T TO Technical Training Organization

37. Example 2: Reading a 32-bit Value - 4 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 1 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 1  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 8000 00001234 5678 xxx1 HD 16 1234 5678 12345678 HR/ W 5678 Host Data T TO Technical Training Organization

38. Example 2: Reading a 32-bit Value - 5 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 1 5. HSTRB 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 1 5. HSTRB  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 1234 5678 xxx1 1234 5678 12345678 8000 0000 HD 16 HR/ W HSTRB 5678 Host Data T TO Technical Training Organization

39. Example 2: Reading a 32-bit Value - 6 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 8000 00001234 5678 xxx1 HD 16 1234 5678 12345678 HR/ W HSTRB 1234_5678 Host Data T TO Technical Training Organization

40. HRDY Example 2: Reading a 32-bit Value - 6 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234 4. HCNTL[1:0] = 11 b (HPID) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234  C Read 8000_0000  C Read 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory...... HPIC 8000 00001234 5678 xxx1 HD 16 1234 5678 12345678 HR/ W HSTRB 1234_5678 Host Data T TO Technical Training Organization

41. Objectives HPI Overview HPI on the DSK Host Software Example HPI Hardware Description Setup Control and Address Writing 32-bits Reading 32-bits  Sequential Accesses  Optional Discussions T TO Technical Training Organization

42. Example 3: Sequential Accesses - 1 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0  C Read 16 values starting at 8000_0000  C Read 16 values starting at 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory HPIC 1234 5678...... 1111 0000 xxx1 HR/ W T TO Technical Training Organization

43. Example 3: Sequential Accesses - 2 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB  C Read 16 values starting at 8000_0000  C Read 16 values starting at 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL HPIA 80000000 Memory HPIC 1234 5678...... 1111 0000 xxx1 HR/ W HSTRB T TO Technical Training Organization

44. Example 3: Sequential Accesses - 3 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB 3. HRDY is high until HD = 5678, HPIA is incremented 1. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 2. HSTRB 3. HRDY is high until HD = 5678, HPIA is incremented  C Read 16 values starting at 8000_0000  C Read 16 values starting at 8000_0000 ‘C6x HPI HPID DMA Aux. Ch. 8000 0000 Addr. Data HHWIL 2 HCNTL HPIA 8000 Memory HD 16 HPIC 1234 5678...... 1111 0000 xxx1 HR/ W HSTRB HRDY  5678 Host Data 1234 5678 12345678 00000004 T TO Technical Training Organization

45. Example 3: Sequential Accesses - 4 4. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234 4. HCNTL[1:0] = 10 b (HPID w/HPIA++) HR/ W = 1 Read value: HHWIL = 0 5. HSTRB 6. HD = 1234  C Read 16 values starting at 8000_0000  C Read 16 values starting at 8000_0000 ‘C6x DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL Memory HD 16 8000 0000 1234 5678...... 1111 0000 HPI HPID 12345678 HPIA 80000000 HPIC 0004 xxx1 HR/ W HSTRB 1234_5678 Host Data T TO Technical Training Organization

46. Example 3: Sequential Accesses - 5 7. The new address in HPIA is copied to the DMA. The DMA begins to pre-fetch this address. HRDY is high until the DMA finishes. 7. The new address in HPIA is copied to the DMA. The DMA begins to pre-fetch this address. HRDY is high until the DMA finishes.  C Read 16 values starting at 8000_0000  C Read 16 values starting at 8000_0000 ‘C6x DMA Aux. Ch. Addr. Data HHWIL 2 HCNTL Memory HD 16 8000 0000 1234 5678...... 1111 0000 HPI HPID 12345678 HPIA 80000000 HPIC 0004 xxx1 HR/ W HSTRB 1234_5678 Host Data 8000 0004 1111 0000 HRDY  0008 T TO Technical Training Organization

47. HPI Pin Summary ‘C6x Host HCNTRL [1:0] HHWIL Address HR/ W R/ W HDS1 HDS2 HCS DATASTROBES HAS ALE HBE [1:0] BE HRDY Ready HINTINTERRUPT HDData [15:0] HSTRB T TO Technical Training Organization

48. HPI Pin Summary ‘C6x Host HCNTRL [1:0] HHWIL Address HR/ W R/ W HDS1 HDS2 HCS DATASTROBES HAS ALE HBE [1:0] BE HRDY Ready HINTINTERRUPT HDData [15:0] HSTRB T TO Technical Training Organization

49. HR/ W HSTRB CC CC ‘C62xx HPI DMA Aux. Ch. Addr. Data 2 HCNTL HPID HPIA Memory...... HD 16 HPIC HHWIL HSTRB HDS1 HDS2 HCS HSTRB internal signal 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = x) Write first halfword, then second with HHWIL = 0, then 1. 2. HSTRB to indicate active. 1. Use HCNTL[1:0] = 00 b to enable access to HPIC HR/ W to write (0). HD = ctrl bits (HWOB = x) Write first halfword, then second with HHWIL = 0, then 1. 2. HSTRB to indicate active. HSTRB T TO Technical Training Organization

50. HAS  Facilitates interface to multiplexed address and data buses by allowing more time to switch bus states from address to data information  Allows HCNTL[1:0], HR/W, and HHWIL to be removed earlier in the access cycle  Often connected to ALE from µC T TO Technical Training Organization

51. Interface Example ‘C6x MC68360 HCNTRL [1:0] HHWIL HR/ W R/ W HDS1 HDS2 HCS DSACK1 HAS HBE [1:0] HRDY HINTIRQx HD [15:0] Data [31:16] A [3:2] A [1] DSACK0 VccGND CSx GND Vcc T TO Technical Training Organization

52. HPI Hardware Overview Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses  Optional Discussions Objectives Control Register (and CSL for HPI) Expansion Bus (XBUS) Next Chapter 17. Wrap Up T TO Technical Training Organization

53. HPI Control Register Interrupts DSPINThost interrupt to ‘6x HINT ‘6x can interrupt Host, determines the state of HINT output HWOB 0 - Big Endian 1 - Little Endian Software Handshaking FETCH requests a read at the address pointed to by HPIA HRDY Ready signal to host. Host can poll this bit to determine the state of the HPI. HWOBDSPINTHINTHRDYFETCH reserved 0123415 5 HWOBDSPINTHINTHRDYFETCH reserved 161718192031 21 T TO Technical Training Organization

54. CSL HPI Support Syntax HPI_getDspint HPI_getEventId HPI_getFetch HPI_getHint HPI_getHrdy HPI_getHwob HPI_setDspint HPI_setHint HPI_SUPPORT Type F C Description Reads the DSPINT bit from the HPIC register Obtain the IRQ event associated with the HPI device Reads the FETCH flag from the HPIC register and returns its value. Returns the value of the HINT bit of the HPIC Returns the value of the HRDY bit of the HPIC Returns the value of the HWOB bit of the HPIC Writes the value to the DSPINT field of the HPIC Writes the value to the HINT field of the HPIC A compile time constant whose value is 1 if the device supports the HPI module Note: F = Function; C = Constant; S = Structure; T = Typedef T TO Technical Training Organization

55. HPI Hardware Overview Setup Control and Address Writing 32-bits Reading 32-bits Sequential Accesses  Optional Discussions Objectives Control Register (and CSL for HPI) Expansion Bus (XBUS) Next Chapter 17. Wrap Up T TO Technical Training Organization

56. Expansion Bus (XBUS)  Overview  HPI  32-bit Slave  Sync/Master  I/O Ports  Async  Sync  XBUS Summary T TO Technical Training Organization

57. ‘C6xxx XBUS Introduction 16-bit wide EPROM SDRAM EMIF Data[31:0] T TO Technical Training Organization

58. ‘C6xxx Who gets the bus? Read FIFO Write FIFO Host 16-bit wide EPROM SDRAM EMIF Data[31:0] T TO Technical Training Organization

59. ‘C6xxx Who gets the bus? Read FIFO Write FIFO Host 16-bit wide EPROM SDRAM EMIF Data[31:0] Are there any problems with this many devices on one bus? Are there any problems with this many devices on one bus? T TO Technical Training Organization

60. C6000 Solution Sync Read FIFO Sync Write FIFO Host 16-bit wide EPROM SDRAM EMIF Data[31:0] XBUS HPI I/O Ports XD[31:0] T TO Technical Training Organization

61. Expansion Bus (XBUS)  Overview  HPI  32-bit Slave  Sync/Master  I/O Ports  Async  Sync  XBUS Summary T TO Technical Training Organization

62. Expansion Bus (XBUS) CC CC ‘C6201 HPI HPID HHWIL 2 HCNTL HPIA HD 16 HR/ W HPIC HSTRB HRDY  2 HBE CC CC C6000 XBUS C6000 XBUS XD 32 The C6000 XBUS provides a 32-bit async interface to the host. XCNTL XR/W XCS XRDY 4 XBE The ‘C6201 HPI provides a 16-bit async interface to the host. In both interfaces, the ‘C6x is slave only. XBD XBISA T TO Technical Training Organization

63. C6000 XBUS Sync Mode - Slave CC CC C6000 XBUS XCLKIN XD [31:0] XW/R XBE [3:0] XBLAST XRDY XCNTL XCS XAS SLAVE XBISA XBD T TO Technical Training Organization

64. C6000 XBUS Synch Mode - Master PCI C6000 XBUS XCLKIN XD [31:0] XW/R XBE [3:0] XBLAST XWAIT XAS XRDY SLAVE XBISA MASTER XBIMA XBEA XBD T TO Technical Training Organization

65. XBUS Synch Mode - Arbitration PCI C6000 XBUS XHOLD XHOLDA XBOFF SLAVE XBISA XBD MASTER XBIMA XBEA XBD XCLKI N XD [31:0] XW/R XBE [3:0] XBLAST XRDY XCNTL XCS XAS XWAIT ARBITER Shared signals T TO Technical Training Organization

66. Expansion Bus (XBUS)  Overview  HPI  32-bit Slave  Sync/Master  I/O Ports  Async  Sync  XBUS Summary T TO Technical Training Organization

67. XBUS I/O Ports HPI Sync or Async XCE0 XCE1 XCE2 XCE3 mem map 4000_0000 5000_0000 6000_0000 7000_0000 8000_0000 Internal Data T TO Technical Training Organization

68. XBUS HPI I/O Ports Sync or Async XCE0 XCE1 XCE2 XCE3 mem map 4000_0000 5000_0000 6000_0000 7000_0000 8000_0000 Internal Data What types of devices can go here? T TO Technical Training Organization

69. I/O Ports 4000_0000 5000_0000 6000_0000 7000_0000 Write Sync FIFO Read Sync FIFO Async Bit I/O XCE0 XCE1 XCE2 XCE3 XCE Control Regs 010 101 xxx 101 010 101 Async Sync MTYPE Data (XD31:0) T TO Technical Training Organization

70. Expansion Bus (XBUS)  Overview  HPI Block  32-bit Slave  Sync/Master  I/O Ports  Async  Sync  XBUS Summary T TO Technical Training Organization

71. HPI PortAsyncSync XCE0 XCE1 XCE2 XCE3 XBUS Summary 16 word addresses 16 read/16 write Master/SlaveSlave only Async Glue Write16 R/W Write16 R/W Write16 R/W Read16 R/W No GlueGlue No GlueGlue No GlueGlue No Glue T TO Technical Training Organization

72. ti Technical Training Organization T TO Technical Training Organization

73. Byte Enable  C Write by byte  C Write by byte ‘C6x HPI DMA Aux. Ch. Addr. Data 2 HCNTL HPID HPIA Memory...... HD 16 HPIC HHWIL 2 HBE ABCD xxx1 HRDY HR/ W HSTRB 80000000  HPIA is a 30-bit word address, lower 2-bits always read as 0  On Host write accesses, these bits are provided by HBE [1:0]  HPIA, HHWIL and HBE [1:0] form a byte address from host  HBE [1:0] are used for writes only  HPIA is a 30-bit word address, lower 2-bits always read as 0  On Host write accesses, these bits are provided by HBE [1:0]  HPIA, HHWIL and HBE [1:0] form a byte address from host  HBE [1:0] are used for writes only T TO Technical Training Organization

74. Writing a Byte HPI 16 HD HBE1 HBE0 HPID BE Write 0xFF to byte 0 of HPID FF?? 01 T TO Technical Training Organization

75. Writing a Byte HPI 16 HD HBE1 HBE0 FF 1 0 1 1 HPID BE Write 0xFF to byte 0 of HPID ?? T TO Technical Training Organization

76. Writing a Halfword HPI 16 HD HBE1 HBE0 FF 00 HPID BE Write 0xFFFF to the HPID FF T TO Technical Training Organization

77. Writing a Halfword HPI 16 HD FF 1 0 1 0 HPID Write 0xFFFF to the HPID FF?? HBE1 HBE0 BE T TO Technical Training Organization

78. C6000 XBUS Summary 16-bit wide EPROM SDRAM EMIF Data[31:0] CE2 CE1 T TO Technical Training Organization

79. C6000 XBUS Summary Sync Read FIFO Sync Write FIFO 16-bit wide EPROM SDRAM Sync Host EMIF Data[31:0] CE2 CE1 XD[31:0] XCS/XAS XCE0 XCE3 XBUS HPI I/O Ports T TO Technical Training Organization

80. Synch or Asynch - XCE Control Reg. 31 16 MTYPE 15 640 RW, +010 010b = 32-bit wide Asynch 101b = 32-bit wide FIFO Note: all others reserved 010b = 32-bit wide Asynch 101b = 32-bit wide FIFO Note: all others reserved T TO Technical Training Organization

81. Asynchronous Interface Read Setup Write Hold Write Strobe Write Setup 3128272221 20 1916 Read Hold rsv MTYPE rsv Read Strobe 15141387643210 RW, + 111111 R, +xRW, +11 RW, +1111RW, +111111RW, +11RW, +1111  What does this remind you of?  An async XCE space is identical to the async EMIF  If FIFO interface is selected, only MTYPE is used T TO Technical Training Organization

82. Synchronous Write Interface EB XFCLK XD[31:0] XRE XOE XWE XCE3 XCE2 XCE1 XCE0 EXT_INTx WF WEN WCLK EF / FF / HF D[31:0] T TO Technical Training Organization

83. Synchronous Read Interface EB XFCLK XD[31:0] XRE XOE XWE XCE3 XCE2 XCE1 XCE0 EXT_INTx RF REN RCLK OE EF / FF / HF Q[31:0] Note: XOE is only enabled in XCE3 for a glueless read interface. T TO Technical Training Organization

84. Synchronous Interface EB XFCLK XD[31:0] XRE XOE XWE XCE3 XCE2 XCE1 XCE0 EXT_INTx WF WEN WCLK EF / FF / HF D[31:0] RF REN RCLK OE EF / FF / HF Q[31:0] Note: XOE is only enabled in XCE3 for a glueless read interface. T TO Technical Training Organization

85. C6000 HPI Expansion Bus I/O Ports XCE0 XCE1 XCE2 XCE3 Sync or Async HPI Sync or Async? T TO Technical Training Organization

86. C6000 Expansion Bus Block Diagram XCLKIN XFCLK XD[31:0] Shared Signals XCE[3:0] XBE[3:0] /XA[5:2] XOE I/O Ports XRE XWE XCS XAS XCNTL Host Port InterfaceXW/R XRDY XBLAST XBOFF XHOLD XHOLDA Bus Arbitration Signals T TO Technical Training Organization

87. C6000 DMA Aux. Channel C6000 XBUS SLAVE XBISA XBD MASTER XBIMA XBEA XBD DMA Aux Ch addr ‘6202 Mem Host data addr data The XBUS as the master writes to the host. The DMA Aux Ch is used to service the request of the XBUS to the ‘C6x mem map. T TO Technical Training Organization

88. C6000 DMA Aux. Channel C6000 XBUS SLAVE XBISA XBD MASTER XBIMA XBEA XBD DMA Aux Ch addr count C6000 Mem Host data addr data Where does the DMA’s count come from??? T TO Technical Training Organization

89. XBUS HPI Control Register (XBHC) XFRCT 3116 rsv 156543210 R, + 0000 0000 00 RW, +0RW, +11RW, +0 RW, +0000 0000 0000 0000 rsv START 01 - starts a write burst *XBIMA to *XBEA 10 - starts a read burst *XBEA to *XBIMA XFRCT Transfer counter when XBUS is master XFRCT Transfer counter when XBUS is master INTSRC 10 - interrupt is caused when XFRCT=0 01 - DSPINT is the interrupt source DSPINT External master to DSP interrupt DSPINT External master to DSP interrupt T TO Technical Training Organization

90. The ‘6202 Expansion Bus  32-bits wide  2 co-existing interfaces  I/O Port  Host Port Interface  Support for PCI interface chips  Support for clocked FIFOs T TO Technical Training Organization

91. C6000 I/O Port  2 modes selected by XCE space  Asynchronous  Similar to EMIF Async. Interface  4 address lines for glueless access to 16 devices  Synchronous FIFOs  Glueless to 3 write/1 read, or 4 write FIFOs  Read in XCE3 only  Minimal glue allows up to 16 write and 16 read FIFOs per XCE space T TO Technical Training Organization

92. Summary HCNTL HCNTL1 HCNTL0Description 00HPIC 01HPIA 10HPID (HPIA++) 11HPID HWOBDSPINTHINT HRDY FETCH reserved 0123415 5 HWOBDSPINTHINT HRDY FETCH reserved 161718192031 21 HSTRB HDS1 HDS2 HCS HSTRB internal signal T TO Technical Training Organization

93. C6000 HPI  Either synchronous or asynchronous  Asynchronous  Slave only operation  Used with hosts which have an async. bus  Very similar to ‘6201 HPI operation  Synchronous  Master and Slave operation  Internal Arbiter for bus arbitration  Connectivity of HPI to DSP mem. map provided by DMA aux. ch. T TO Technical Training Organization

94. Lab 16 (Optional) T TO Technical Training Organization

95. Writing a Byte  C Write by byte  C Write by byte ‘C6x HPI DMA Aux. Ch. Addr. Data 2 HCNTL HPID HPIA Memory...... HD 16 HPIC HHWIL 2 HBE ABCD ByteHHWIL = 0HHWIL = 1LE addr.BE addr. D10110011 D CBA C01110110B1110 01A11011100 xxx1 HRDY HR/ W HSTRB 80000000 T TO Technical Training Organization

96. Writing a Halfword  C Write by halfword  C Write by halfword ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC H-wordHHWIL = 0HHWIL = 1LE addr.BE addr. B00110010A11001000 BA AB xxx1 2 HCNTL HD 16 HHWIL 2 HBE HRDY HR/ W HSTRB 80000000 T TO Technical Training Organization

97. Writing a Word  C Write by word  C Write by word ‘C6x HPI DMA Aux. Ch. Addr. Data HPID HPIA Memory...... HPIC WordHHWIL = 0HHWIL = 1LE addr.BE addr. A00 A A xxx1 2 HCNTL HD 16 HHWIL 2 HBE HRDY HR/ W HSTRB 80000000 T TO Technical Training Organization

98. Timing 1. Use HCNTL[1:0] = 00 b to setup HPIC HR/W- to write (0). Write first halfword, then second. HHWIL = 0, then 1. 2. HSTRB to indicate active. 3. HRDY from HPI to host, “got it” 1. Use HCNTL[1:0] = 00 b to setup HPIC HR/W- to write (0). Write first halfword, then second. HHWIL = 0, then 1. 2. HSTRB to indicate active. 3. HRDY from HPI to host, “got it”