1. Priority encoder

2. Overview Priority encoder- theoretic view Other implementations The chosen implementation- simulations Calculations and comparisons

3. The target of the project Building priority encoder using the multilevel lookahead and folding techniques

4. Uses of priority encoding INR - interconnection network router design of SAE – sequential address encoder of a content associate memory (CAM) microcontroller and microprocessor (incrementer / decrementer)

5. basic concepts of priority encoders The i-th output bit EP i = D i * P i D i - the input data P i - the priority token passed into this bit the relationship between P i and P i-1 P i = D i-1 * P i-1 the generated EP i is EP i = D i * D i-1 * D i-2 … D 1 * D 0

6. Different implementations For 4 bit priority encoder

7. matrix Because of a minimal distance needed between the lines the layout is large and complicated. Sum of minterms, the straight-forward implementation

8. Basic units The structure is build from equal units. Each unit calculates y i and x pi for the i-th bit

9. Then, by chaining the units we construct the output In this implementation we save silicon area, but pay in propagation delay

10. tree Tree of multiplexers implemented by butterflies Efficient implementation in area and power, has longer propagation then the folding technique

11. the multilevel lookahead structure The output third-level lookahead signal of the ith 8-bit macro is: LA3 i|i= 0~n-1 = D 8i+7 + D 8i+6 + D 8i+5 + D 8i+4 + D 8i+3 + D 8i+2 + D 8i+1 + D 8i + LA3 i-1 LA3 -1 = 0 n = N/8 N – number of input bits The ith 4-bit sub macros LA2 i = D 8i+3 +D 8i+2 +D 8i+1 +D 8i + LA3 i-1

12. EP 8i = D 8i * LA3 i-1 EP 8i+1 = D 8i+1 * D 8i * LA3 i-1 EP 8i+2 = D 8i+2 * D 8i+1 * D 8i * LA3 i-1 EP 8i+3 = D 8i+3 * D 8i+2 * D 8i+1 * D 8i * LA3 i-1 EP 8i+4 = D 8i+4 * LA2 i EP 8i+5 = D 8i+5 * D 8i+4 * LA2 i EP 8i+6 = D 8i+6 * D 8i+5 * D 8i+4 * LA2 i EP 8i+7 = D 8i+7 * D 8i+6 * D 8i+5 * D 8i+4 * LA2 i The 8-bit macro formulas

13. 8-bit macro cell

14. Diagram of 32-bit chain designed encoder

15. The folding technique- first level folding The LA3 i that generated by the macro with the higher priority can be connected to other macros with lower priority. Such connection can make the critical path shorter In this connection we’ll lose the advantage in layout arrangement and wiring complexity

16. We’ll connect LA3 0 to the second and the fourth macros (not to the third) and we’ll get 2x2 matrix in this way the fourth macro is connected to 2 neighboring macros the number of gate delays is reduced to 4 (<log 2 32 ) Folding - implementation

17. Block diagram of a 32-bit priority encoder with folding

18. 64 bit priority encoder with first level folding

19. Multilevel folding In order to reduce the gate delay to be less then log 2 N in grater priority encoders, we can apply the folding technique again & again for example : N=128 First-Level folding : 8 gate delay Second-Level folding : 7 gate delay Third-Level folding :<7 gate delay

20. 64-bit priority encoder with 2 levels of folding

21. For 256-bit priority encoder the new design can achieve about 10 times performance while spending ½ power consumption.

22. The implementation We decided to implement the project using bottom up architecture, starting with a 1 bit unit. Each stage will be checked separately. Moving to the next stage is only after the previous stage is finished

23. 1 bit unit At first we implemented 1 bit unit and checked it. The circuit:

24. The simulation: The output Lookahead bit The input The clock

25. The 4 – bit unit The 4 bit unit circuit:

26. The input signals:

27. The outputs: When the lookahead high all the outputs equals zero Lookahead outputs

28. The 8-bit unit

29. The output signals v0 v3 Not valid

30. The next lookahead v4 v7

31. The 32-bit chain encoder

32. The results

33. The problem we encountered “glitches”

34. The “glitch” clock rising the glitch starts after clock rising

35. The widest glitch comes at higher bits clock Bit #60

36. 32 bit-folding

37. 64 bit first level folding

38. 64 bit second level folding

40. 64 bit second level folding with one critical path

41. Propagation delay - reduction To minimize the propagation delay of the EP we made the following changes : -Reduced the clock period from 200ns to 20ns. -Divide the clock pulse to different periods for low time and high time. Those changes made under the constrains of : -Keeping the high pulse length 80% of the base pulse. -Making sure all the requested changes and currents are stable before clock raising. -The optimum result we conclude for the clock period: 5ns for low time and 15ns high time.

42. Results – 32 bit

43. Results – 64 bit

44. Results – 64 bit (high)

45. 80% high pulse

46. The vhdl simulation

47. The vhdl simulation of a 32 bit priority encoder Here the lsb of input changes from 0 to 1, and the output changes

49. Compare table unitmatrixtreefolding Area [ mm² ] 0.076 0.0430.053 Power [ 10^-11fw ] 149.6173.4112.8127.5 Time [ns] 241.275188