1. 1 68HC11 Timer HC11 or HC12: Chapter 10

2. 2 68HC11 Timer Subsystem  Several timing functions: Basic timing Basic timing Real time interrupts Real time interrupts Output compare Output compare Input capture Input capture Computer Operating Properly Computer Operating Properly Pulse Accumulator Pulse Accumulator Pulse Width Modulation Pulse Width Modulation  Common Features Based on a central timer Based on a central timer Overflow Flags Overflow Flags Interrupt Enables Interrupt Enables

3. 3 Timer System Block Diagram Reference Manual p. 370

4. 4 Basic Timer

5. 5 Basic Timer– TCNT $100E  16-bit free running counter (timer) Cannot be set or stopped. Cannot be set or stopped.  E-clk = bus clock = ¼ XTAL Clock (crystal)  Can be prescaled by 1,4,8, or 16  Read only at memory address $100E:100F Overflow flag is bit 7 in TFLG2 ($1025) Overflow flag is bit 7 in TFLG2 ($1025)  Can use overflow to extend counter’s range Timer Overflow Interrupt Enable Timer Overflow Interrupt Enable  Bit 7 in TMSK ($1024)

6. 6 TCNT - $100E:$100F Timer Counter Register 76543210 Bits CNT15 READ ONLY Register CNT13CNT12CNT11CNT10CNT9CNT8 CNT14 76543210 CNT7 CNT5 CNT4CNT3CNT2CNT1CNT0CNT6 $100E $100F

7. 7Prescaler 76543210 Bits PR0 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024 -- TMSK2 PR1,PR0 = Timer prescale select Timer Clock = E-Clock / Prescale Factor PR1 PR0 Prescale Factor 0 0 1 0 1 2 1 0 4 1 1 16 Notes:1.) Unlike HC12, HC11 Prescaler must be set with 64 clock cycles of RESET 2.) The Buffalo Monitor initializes the prescaler to 1 on our lab boards

8. 8 Timer Overflow Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) TOF = Timer overflow flag - 0 = No overflow 1 = Overflow TOF is reset to 0 by writing ‘1’ to TOF

9. 9 Timer Overflow Interrupts 76543210 Bits PR2 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024 (TMSK2) TOI = Timer overflow interrupt enable 0 = disable interrupt 1 = enable interrupt

10. 10 Basic Timer Example  Problem: Write an ISR to read the input from PortC and write it to PortB approximately every 1,000,000 clock cycles. Assume timer prescale = 1

11. 11 Basic Timer Example Main Program  Set Timer Overflow Interrupt Vector ORG TOI_VECTOR ($FFDE:FFDF) ORG TOI_VECTOR ($FFDE:FFDF) FDB TO_ISR FDB TO_ISR  Configure Timer Overflow Interrupt TMSK2(7)  ‘1’ TMSK2(7)  ‘1’  Enable Interrupts (CLI)  Wait for interrupts

12. 12 Basic Timer Example TO_ISR  Disable Interrupts SEI SEI  Turn-off Interrupt Request TOF  ‘1’ TOF  ‘1’  CNT = CNT + 1  IF CNT = MAX_CNT then CNT = 0 CNT = 0 A  PORTC A  PORTC PORTB  A PORTB  A  END IF  Return from Interrupt

13. 13 Basic Timer Example MAX_CNT Calculation  Need to wait 1,000,000 (or $F4240) E-clock cycles.  Interrupt is generated every 65536 or $10000 clock cycles  Max_CNT = INT(1,000,000 / 65556) = 15.258 ~ 15 = $F Note: INT($F4240/$10000) = $F Note: INT($F4240/$10000) = $F  Set MAX_CNT EQU $F

14. 14 In-Class Assignment  The evaluation board used in lab uses and 8 MHz crystal to set the XTAL clock frequency  The Buffalo ROM Monitor sets the prescale to 1 (PR1, PR0 = 0, 0) 1.Determine the frequency of the E-Clock 2.Determine the time period between timer overflow interrupts (TOI) 3.If the previous example was implemented on the lab board, what would the time interval (in seconds) between successive transfers from Port C to Port B?

15. 15 Real Time Interrupt

16. 16 Real Time Interrupt  Similar to Timer Overflow Interrupt except  We have: RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) System E-Clock is first divided by $2000 (8192 10 ) using a 13-bit clock, and then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026) System E-Clock is first divided by $2000 (8192 10 ) using a 13-bit clock, and then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026) RTR1 and RTR2 can be set anytime in the program RTR1 and RTR2 can be set anytime in the program

17. 17 Real Time Interrupt Enable 76543210 Bits PR2 PR1PAII00PAOVIRTIITOI Timer Interrupt Mask Register 2: $1024 (TMSK2) RTII = Real Time Interrupt Enable 0 = disable interrupt 1 = enable interrupt

18. 18 Real Time Interrupt Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) RTIF = Real Time Interrupt flag - 1 = RTI has occurred RTIF is reset to 0 by writing ‘1’ to RTIF

19. 19 Real Time Interrupt Prescale 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 RTR1, RTR0= Real Time Interrupt Prescale RTR1 RTR0 Prescale Value Nominal RTI period (2MHz E-Clock) 0 0 14.096 ms 0 1 28.192 ms 1 0 416.384 ms 1 1 832.768 ms Port A Control Register: $1026 (PACTL)

20. 20 In-Class Assignment Get with a partner to complete the following tasks: 1.Explain the difference between the RTI and the basic Timer Overflow. 2.Assume an E-clock of 1 MHz. Determine the values needed for RTR1 and RTR0 to provide a RTI as close as possible to 10 ms

21. 21 Computer Operating Properly COP

22. 22 Computer Operating Properly COP  Also known as a “watchdog” timer When enabled, your program must set the COP timer and reset the COP timer prior to the COP’s “time-out” delay. This time-out delay is programmable. When enabled, your program must set the COP timer and reset the COP timer prior to the COP’s “time-out” delay. This time-out delay is programmable. If the program does not set or reset the COP timer before the “time-out”, a COP failure interrupt is generated and the ISR assigned to the interrupt is executed. If the program does not set or reset the COP timer before the “time-out”, a COP failure interrupt is generated and the ISR assigned to the interrupt is executed.

23. 23 Computer Operating Properly COP  Usage Design your program to set and reset the COP before time-out. Design your program to set and reset the COP before time-out. If your program enters an infinite loop, the COP timer will “time-out” automatically causing a COP failure interrupt. If your program enters an infinite loop, the COP timer will “time-out” automatically causing a COP failure interrupt. Use the COP failure ISR to place your system into a “safe” mode or restart mode. Use the COP failure ISR to place your system into a “safe” mode or restart mode.

24. 24 Output Compare

25. 25 Timer Output Compare  Using the timer overflow flag or interrupt will generate a count every 65536 clock cycles.  Given a 2 MHz E-clock, this gives a sample resolution of 32.8 ms (prescale = 1)  The timer output compare feature allows for more precise timing.

26. 26 Timer Output Compare  There are five output compare registers  Each with a separate Compare Counter Compare Counter Interrupt Mask Interrupt Mask Overflow Flag Overflow Flag

27. 27 TOC1 – TOC5 Timer Output Compare Registers 76543210 Bits OCn15 TOC1 - $1016:$1017 TOC2 - $1018:$1019 TOC3 - $101A:$101B OCn13OCn12OCn11OCn10OCn9OCn8 OCn14 76543210 OCn7 OCn5OCn4OCn3OCn2OCn1OCn0 OCn6 TOC4 - $101C:$101D TOC5 - $101E:$101F

28. 28 Output Compare Flags 76543210 Bits IC3F IC2FOC4FIC1FOC5FOC3FOC2FOC1F Main Timer Interrupt Flag Register 1: $1023 (TFGL1 ) OC1F-OC5F = Output Compare Flags 1 = when output compare register equals TCNT 0 = reset by writing ‘1’ to bit position

29. 29 Output Compare Interrupts 76543210 Bits IC3I IC2IOC4IIC1IOC5IOC3IOC2IOC1I Main Timer Interrupt Mask Register 1: $1022 (TMSK1) OC1I-OC5I = Output Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

30. 30 Output Compare Example  Problem: Write an ISR to read the input from PortC and write it to PortB approximately every 10,000 E-clock cycles. Assume timer prescale = 1  Note: 10,000 cycles is less than one timer overflow!!

31. 31 Output Compare Example Main Program  A  TCNT ; Load current count  TOC1  A + 10000 ; Add 10000 to current count  Configure Output Compare 1 Interrupt TMSK1(7)  ‘1’ TMSK1(7)  ‘1’  Enable Interrupts (CLI)  Repeat  Until Forever  Set Output Compare 1 Interrupt Vector ORG OC1_VECTOR ($FFE8:FFE9) ORG OC1_VECTOR ($FFE8:FFE9) FDB OC1_ISR FDB OC1_ISR

32. 32 Output Compare Example OC1_ISR  Disable Interrupts SEI SEI  Turn-off Interrupt Request OC1F  ‘1’ OC1F  ‘1’  A  PORTC  PORTB  A  A  TCNT ; Load current count  TOC1  A+10000 ; update TOC1 for next  interrupt  Return from Interrupt

33. 33 In-Class Assignment Get with a partner and answer the following: Assume an E-clock of 1 MHz and prescale set to 4. Determine what number must be added to the current TCNT (sum store in TOC1) to create an interrupt that occurs in 125 msec.

34. 34 Input Capture

35. 35 Timer Input Capture 16-bit TCIx Latch Det Ckt TCNT clk Ext Signal When the Ext Signal is detected on pin PAx, the current value of the free running counte TCNT is latched into the timer input capture latch. This value can be read and saved to determine the time between events. PAx

36. 36 Timer Input Capture  The timer input capture feature can be used to time external events  Three input capture registers TIC1 : $1010:$1011 TIC1 : $1010:$1011 TIC2 : $1012:$1013 TIC2 : $1012:$1013 TIC3: $1014:$1015 TIC3: $1014:$1015  Maximum time between events must be less than 65536 cycles

37. 37 TIC1 – TIC3 Timer Input Capture Registers 76543210 Bits ICn15 TIC1 - $1010:$1011 TIC2 - $1012:$1013 TIC3 - $1014:$1015 ICn13ICn12ICn11ICn10ICn9ICn8 ICn14 76543210 ICn7 ICn5ICn4ICn3ICn2ICn1ICn0 ICn6

38. 38 Input Compare Interrupts 76543210 Bits IC3I IC2IOC4IIC1IOC5IOC3IOC2IOC1I Main Timer Interrupt Mask Register 1: $1022 (TMSK1) IC1I-IC3I = Input Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

39. 39 Interrupt Capture Flags 76543210 Bits IC3F IC2FOC4FIC1FOC5FOC3FOC2FOC1F Main Timer Interrupt Flag Register 1: $1023 (TFGL1 ) IC1F-IC3F = Interrupt Capture Flags 1 = when selcted edge is detected 0 = reset by writing ‘1’ to bit position

40. 40 Timer Control Register 2 TCTL2 - $1021 76543210 Bits EDG1BEDG1AEDG2BEDG2AEDG3BEDG3A00 EDGnB EDGnA Configuration 0 0 Disabled 0 1 Rising Edge 1 0 Falling Edge 1 1 Either Edge

41. 41 Pulse Accumulator

42. 42 Pulse Accumulator  The pulse accumulator can be used as an event counter. That is, it can count the number of external events.  Note: difference to Timer Input Capture which counts the time between external events.  Configuration: PACTL ($1026) is used to configure PA PACTL ($1026) is used to configure PA PACNT ($1027) is the PA Count Register PACNT ($1027) is the PA Count Register  Two Modes: Event Counting: PA7 is External Clock Event Counting: PA7 is External Clock Gated Time Accumulation: PA7 is enable to system clock divided by 64 Gated Time Accumulation: PA7 is enable to system clock divided by 64

43. 43 PACTL: $1026 Port A Control Register 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 PAEN6 = Pulse Accumulator System Enable 0 = Disable (Default) Port A is set for I/O function 1 = Enable Port A is set for Pulse Accumulator function PAMOD= Pulse accumulator mode 0 = Event counter (Default) 1 = Gated time accumulation

44. 44 PACTL: $1026 Port A Control Register 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 PEDGE= Pulse Accumulator Edge Select 0 = Falling Edge (in event mode) – Active High (in gated mode) 1 = Rising Edge (in event mode) – Active Low (in gated mode)

45. 45 Pulse Accumulator Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) PAOVF = Pulse Accumulator Overflow Flag 1 = Overflow has occurred PAOVF is reset to 0 by writing ‘1’ to PAOVF PAIF = Pulse Accumulator Input Edge Flag 1 = Input edge has been detected PAIF is reset to 0 by writing ‘1’ to PAIF

46. 46 Pulse Accumulator Interrupts 76543210 Bits PR2 PR1PAII00PAOVIRTIITOI Timer Interrupt Mask Register 2: $1024 (TMSK2) PAOVI = Pulse Accumulator overflow interrupt enable 0 = disable interrupt 1 = enable interrupt PAII = Pulse Accumulator input edge interrupt enable 0 = disable interrupt 1 = enable interrupt

47. 47 Pulse Width Modulation

48. 48 Pulse Width Modulation  Some versions of 68HC11 have a pulse width modulation (PWM) module which can be used to generate periodic output waveforms with a specific period and duty cycle (i.e. the percentage of time the signal is high compare to when it is low).  Example application: PWM for controlling motor speed in a robot

49. 49 Timer Summary  Timer subsystem – most complex in 68HC11  Based on free running timer  Timings available: Basic timing Basic timing Real time interrupts Real time interrupts Output compare Output compare Input capture Input capture Computer Operating Properly Computer Operating Properly Pulse Accumulator Pulse Accumulator Pulse Width Modulation Pulse Width Modulation  Overflow flags and/or Interrupts are available