1. © Copyright Alvarion Ltd. SVA Dafna Senderovich Jan 2006

2. 2 DFV – Design For Verification The capture of designer intent and assumptions in a form directly usable by downstream verification tools. A verification methodology that leverages information captured during RTL specification and implementation. DFV combines the following concepts: Verification-friendly RTL coding standards (and documents) Cross-participation in design & test plan reviews Clean & consistent interfaces at multiple levels of design abstraction (Block-level interfaces tend to be informally defined) Designers specify assertions to capture their intent, communicate their intent to team members and aid verification process Thinking about verification during design

3. 3Assertions Definition: “ A piece of verification code used to check a property” Benefits: Assertions are statements of design assumptions and intentions Detect bugs close to the root cause (pinpointing failure locations in space and time) Increase confidence that the RTL is free of errors (DUT coverage capabilities) Enable verification with formal methods (the same assertions can be used directly by formal tools) Assertions can enhanced the exiting verification method (simulation and formal) by pinpointing design bugs at the source SoC outputs are often symptoms of a bug that occurred many cycles earlier deep inside the chip - Assertion can isolate these bugs

4. 4Methodology Formalize the natural language specification using assertion Write assertion along with the RTL code Ideally, as the designer writes the RTL, he documents assumptions about how the design is expected to behave and about the rules for interfaces with other blocks Use assertions to clarify understanding of the design Create libraries or templates for common assertions Provide hooks in the verification environment to observe and control assertions Provide detailed messages for assertion failures Don’t try to represent the entire function of the design block in a single assertion Don’t use assertions to check timing-dependent or asynchronous behavior

5. 5Assertions Assertion can be used on: Capture protocol requirements on inputs and outputs Document designer intent (illegal state combinations) Ideally, as the designer writes the RTL, he documents assumptions about how the design is expected to behave and about the rules for interfaces with other blocks It can enhanced the exiting verification method (simulation and formal) by pinpointing design bugs at the source

6. 6Questions Who writes the assertions? What languages should we use? What about assertion libraries? How do we debug assertions? How do I know that I have written enough assertions?

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