1. 3 Unit Course, Spring 2001 EECS Department, UC Berkeley Embedded Software Engineering www.eecs.berkeley.edu/~fresco/giotto/course Christoph Kirsch

2. It’s significant

3. It’s tricky

4. It’s risky

5. It’s fun

6. Problem Real-Time Computer System Controlled Object Operator Man-Machine Interface Instrumentation Interface Kopetz97 Methodologies for the implementation of embedded real-time applications Methodology: tool-supported, logical, compositional Implementation: compositional, scalable, dependable

7. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

8. Microcontroller Market Cost Performance

9. Mechatronics Fly-by-wire Drive-by-wire

10. Engine Controller Temporal accuracy of 3μsec Up to 100 concurrent software tasks Hard real-time: no missed deadlines @ 6000rpm, 10ms for 360º 0.1°

11. Video Streaming 25 frames/sec Dynamic resource allocation Soft real-time: degraded QoS

12. Real-Time Systems CharacteristicsHardSoft Response timeHard-requiredSoft-desired Peak-load performance PredictableDegraded Control of paceEnvironmentComputer RedundancyActiveCheckpoint Error detectionAutonomousUser assisted Kopetz97

13. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

14. Concurrency Task1Task2 Host Network Message1 Message2 In addition: Other resource constraints Time constraints

15. Real-Time Not later than Time Time-instantDeadline Duration @ for

16. Real-Time Task fInputOutput Worst case execution time

17. Real-Time Scheduling terminateactivate PassiveActivation Active

18. Off-Line Scheduling terminateactivate PassiveTable Active Static System

19. On-Line Scheduling terminateactivate PassiveAlgorithm Active Dynamic System

20. Non-Preemptive Scheduling ReadyRun schedule terminateactivate PassiveActivation

21. Preemptive Scheduling ReadyRun schedule terminateactivate PassiveActivation preempt

22. Shared Resources ReadyRun Wait schedule preempt terminate busyfree activate PassiveActivation

23. Scheduling Problem Real-Time Scheduling SoftHard Off-lineOn-line PreemptiveNon-preemptive Preemptive

24. Earliest Due Date Time Processors P1P1 T1T1 T5T5 10 T1T1 T2T2 T3T3 T4T4 T5T5 CiCi 11132 didi 3 785 T3T3 T4T4 T2T2 d1d1 d5d5 d3d3 d4d4 d2d2 Buttazzo97

25. Earliest Deadline First Time Tasks T1T1 T5T5 10 T1T1 T2T2 T3T3 T4T4 T5T5 aiai 00236 CiCi 12222 didi 254 9 T3T3 T4T4 T2T2 T2T2 T4T4 Buttazzo97

26. Real-Time Periodic Task fInputOutput Worst case execution time Frequency

27. Rate Monotonic Analysis Time Tasks T1T1 10 T1T1 T2T2 CiCi 21 pipi 5 T2T2 T2T2 T1T1 T1T1 T1T1

28. Scheduling Anomalies T1T1 T9T9 T4T4 T8T8 T7T7 T6T6 T5T5 Time Processors P1P1 P2P2 P3P3 T1T1 T2T2 T3T3 T4T4 T6T6 T7T7 T9T9 12 T5T5 T8T8

29. Shorter Computation Times T1T1 T9T9 T4T4 T8T8 T7T7 T6T6 T5T5 Time Processors P1P1 P2P2 P3P3 T1T1 T2T2 T3T3 T4T4 T6T6 T7T7 T9T9 13 T5T5 T8T8

30. More Processors T1T1 T9T9 T4T4 T8T8 T7T7 T6T6 T5T5 Time Processors P1P1 P2P2 P3P3 P4P4 T1T1 T2T2 T3T3 T4T4 T5T5 T6T6 T7T7 T8T8 T9T9 15

31. Weaker Precedence T1T1 T9T9 T4T4 T6T6 T5T5 Time Processors P1P1 P2P2 P3P3 T1T1 T2T2 T3T3 T4T4 T7T7 T8T8 T9T9 16 T5T5 T6T6

32. Real-Time Communication Network Message1 Message2

33. Real-Time Message mSourceTarget Latency

34. Explicit Flow Control Network Message1 Message2 Send time not known a priori Sender can detect errors

35. Implicit Flow Control Network Message1 Message2 Send time is known a priori Receiver can detect errors

36. Explicit Flow Control: Priority Network Message1 Message2 Medium-Access Protocols: CSMA/CD - LON, Echelon 1990 CSMA/CA - CAN, Bosch 1990 FTDMA - Byteflight, BMW 2000 TDMA - TTP, Kopetz 1993

37. Control Area Network M1M1 M2M2 Time Messages M2M2 M1M1 0 00 0 11 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1

38. Implicit Flow Control: Time Network Message1 Message2 Medium-Access Protocols: FTDMA - Byteflight, BMW 2000 TDMA - TTP, Kopetz 1993

39. Time-Triggered Protocol M1M1 M2M2 Time Network N1N1 M1M1 M2M2 Slot 1 Slot 2

40. Literature RT scheduling: –Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. G. Buttazzo. Kluwer, 1997. RT communication: –Real-Time Systems – Design Principles for Distributed Embedded Applications. H. Kopetz. Kluwer, 1997. –Byteflight, CAN papers.

41. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

42. Concurrency ControlData Task1Task2Task1Task2 Parallel CompositionI/O Decomposition

43. Control Operators ParallelChoice Sequential Loop

44. Real-Time State Time EventFrequency Time Change of state Function

45. Real World Time Data

46. Discrete Data Time d0d0 d1d1 d2d2 Data d3d3

47. State Time State 1 d0d0 State 2 Data State 0 d1d1 d2d2 d0d0 d1d1 d1d1 d2d2 d2d2 d3d3 d3d3

48. Continuous Time Time Interval Start EventTerminating Event t1t1 t2t2 State 1 Data

49. Digital Clock Time Data Granule t1t1 t2t2 Clock Tick @ 1/(t2-t1) Hz

50. Discrete Time Time Data t1t1 t2t2 State 1

51. Event-Triggered (ET) System Time Data Change of state

52. Time-Triggered (TT) System Time Data Clock tick

53. Esterel - Giotto Esterel: –Synchronous reactive language –Event-triggered semantics Giotto: –Time-triggered semantics –Distributed platforms

54. Esterel: Operators Choice:Parallel: P || Qpresent S then P else Q Sequential: P ; QPQ P Q P Q

55. Esterel: Event Event: Time emit S Loop: loop P each SP await S

56. Event - Reaction fEventReaction

57. Esterel: Controller module normal: input A, B, R; output O; loop [ await A || await B ]; emit O each R end module R?R? R?R?R?R? A?.~R?.O! A?.~R?B?.~R? B?.~R?.O! A?.B?.~R?.O!

58. Giotto: Operators Choice:Parallel: ModeProgram Sequential: Task

59. Giotto: Time Sequential: Task Time InputOutput

60. Sensor - Control Law - Actuator fSensorsActuators

61. Giotto: Helicopter Control mode normal ( ) period 20ms { taskfreq 1 do servo = Control ( position ) ; taskfreq 4 do position = Navigation ( GPS, position ) ; }

62. Control @ 50Hz Semantics Task Navigation @ 200Hz msec5101520

63. Input Task msec5101520

64. Computation Task msec5101520 Control LawNavigation Integrator

65. Output Task msec5101520

66. Literature Esterel: –The Foundations of Esterel. G. Berry. In Proof, Language and Interaction: Essays in Honour of Robin Milner. G. Plotkin, C. Stirling and M. Tofte, editors. MIT Press, 2000. –Synchronous programming of reactive systems. N. Halbwachs. Kluwer, 1993. Giotto: –Embedded Control System Development with Giotto. B. Horowitz, T. Henzinger, C. Kirsch. 2000. –Giotto: A Time-Triggered Language for Embedded Programming. B. Horowitz, T. Henzinger, C. Kirsch. 2000.

67. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

68. Concurrency Task1Task2Task1Task2 Parallel CompositionI/O Decomposition Task1Task2; Task1; Task2 Task1

69. Real-Time Task1Task2;;Task1Task3Task2Task1; Time Event DeadlineTime Frequency

70. Control @ 50Hz Helicopter Control Task Navigation @ 200Hz msec5101520

71. Read Task msec5101520 Input

72. Write Task msec5101520 Output

73. Worst Case Execution Time Task msec5101520 Control LawNavigation Integrator

74. Deadline Task msec5101520

75. Code Task msec5101520

76. Literature Some compiler books: –Compilers, Principles, Techniques, and Tools. A.V. Aho, R. Sethi, J.D. Ullman. Addison- Wesley, 1985. –Compiler Design. R. Wilhelm, D. Maurer. Addison- Wesley, 1995.

77. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

78. Real-Time Task fInputOutput Worst case execution time

79. Type Abstract Data Type Interface: Set of methods

80. Empty Abstract Interface Interface: Set of methods

81. Application-dependent Framework Application-dependent Application-independent

82. ? Type vs. Task Interface: Set of methods InputOutput

83. Literature Patterns & Frameworks: –Design Patterns: Elements of Reusable Object Oriented Software. E. Gamma, J. Vlissides, R. Johnson, R. Helm. Addison Wesley, 1994. –Design Patterns for Object-Oriented Software Development. W. Pree, E. Gamma. Addison Wesley, 1995.

84. Embedded Programming …requires the integration of: 1.Real-time scheduling/communication concepts 2.Programming language design 3.Compiler design 4.Classical software engineering techniques 5.Formal methods

85. Formal Verification Time SafetyLiveness Control Data Safety: Wrong things never happen! Liveness: Something useful will happen eventually! Property Space

86. Language Hierarchy Design Model Program Executable Non-Deterministic synthesizeanalyze compile expand Deterministic Sequential Universal Macros Automata Code Machine

87. Non-Determinism ParallelChoice Sequential Non-Determinism A E Programming OperatorsModeling Operator

88. Esterel: Verification EsterelProperty Automata Esterel Abstraction“Bisimulation” Model Checking

89. Esterel: Hierarchy Design Model Esterel Executable Bisimulation compile Non-Det. Automata Deterministic Code Sequential Circuit Model Checking

90. Giotto: Verification GiottoProperty MasaccioAutomata Masaccio Model Checking Abstraction“Refinement”

91. Giotto: Hierarchy ? Masaccio Giotto Executable synthesizeRefinement compile expand Hybrid Modules Deterministic Code Seq. Stack Machine Model Checking

92. Giotto: Hierarchy

93. Literature Esterel: –Papers @ www.esterel.org Giotto: –T.A. Henzinger. Masaccio: A Formal Model for Embedded Components. LNCS 1872, Springer, 2000, pp. 549-563.

94. End