1. CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 8: Documentation and Timing Diagrams José Nelson Amaral

2. CMPUT 329 - Computer Organization and Architecture II2 Reading Sections 5.1, 5.2, 5.3, 5.4, 5.5 (Wakerly Textbook) In this topic we will cover: - Documentation styles - Timing Diagrams - Multiplexers - Decoders - PLAs

3. CMPUT 329 - Computer Organization and Architecture II3 Documentation Standards zBlock diagrams yfirst step in hierarchical design zSchematic diagrams zHDL programs (ABEL, Verilog, VHDL) zTiming diagrams zCircuit descriptions

4. CMPUT 329 - Computer Organization and Architecture II4 Block Diagram

5. CMPUT 329 - Computer Organization and Architecture II5 Schematic diagrams zDetails of component inputs, outputs, and interconnections zReference designators zPin numbers zTitle blocks zNames for all signals zPage-to-page connectors

6. CMPUT 329 - Computer Organization and Architecture II6 Example schematic

7. CMPUT 329 - Computer Organization and Architecture II7 Flat Schematic Structure

8. CMPUT 329 - Computer Organization and Architecture II8 Hierarchical Schematic Structure

9. CMPUT 329 - Computer Organization and Architecture II9 Other Documentation zTiming diagrams yOutput from simulator ySpecialized timing-diagram drawing tools zCircuit descriptions yText (word processing) yCan be as big as a book (e.g., typical Cisco ASIC descriptions) yTypically incorporate other elements (block diagrams, timing diagrams, etc.)

10. CMPUT 329 - Computer Organization and Architecture II10 Gate symbols

11. CMPUT 329 - Computer Organization and Architecture II11 DeMorgan Equivalent Symbols Which symbol to use? Answer depends on signal names and active levels.

12. CMPUT 329 - Computer Organization and Architecture II12 Viewing Gates in Positive or Negative Logic ABAB C=A·B C=1 if and only if A=1 AND B=1 AND A_L B_L C_L=A_L+B_L C=0 if and only if A=0 OR B=0

13. CMPUT 329 - Computer Organization and Architecture II13 Viewing Gates in Positive or Negative Logic C=1 if and only if A=1 OR B=1 C=0 if and only if A=0 AND B=0 OR ABAB C=A+B A_L B_L C_L=A_L·B_L

14. CMPUT 329 - Computer Organization and Architecture II14 Logic Functions: Boolean Algebra INVERTER XX’ If X=0 then X’=1 If X=1 then X’=0 OR ABAB C=A+B If A=1 OR B=1 then C=1 otherwise C=0 ABAB C=A·B If A=1 AND B=1 then C=1 otherwise C=0 AND

15. CMPUT 329 - Computer Organization and Architecture II15 Signal Names and Active Levels xSignal names are chosen to be descriptive. xActive levels -- HIGH or LOW named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name.

16. CMPUT 329 - Computer Organization and Architecture II16 Examples of Buses

17. CMPUT 329 - Computer Organization and Architecture II17 Timing Diagrams

18. CMPUT 329 - Computer Organization and Architecture II18 Timing Diagrams

19. CMPUT 329 - Computer Organization and Architecture II19 Bus Timing Diagram

20. CMPUT 329 - Computer Organization and Architecture II20 Bus Timing Diagram

21. CMPUT 329 - Computer Organization and Architecture II21 Multiplexers 4-to-1 MUX I0I0 I1I1 I2I2 I3I3 AB Z ABI3ABI3 A B’ I 2 A’ B I 1 A’ B’ I 0 Z

22. CMPUT 329 - Computer Organization and Architecture II22 A typical use of a MUX in a processor control path Consider the following sequence of instructions: 0x7F800 add $16, $18, $15 # reg16  reg18 + reg15 0x7F804 beq $8, $0, target # if reg16 == 0 goto target 0x7F808 sub $17, $17 $15 # reg17  reg17 - reg15 PC Add 4 0 1 Branch Target Unit Branch taken Mux

23. CMPUT 329 - Computer Organization and Architecture II23 A 4-to-1 MUX can implem. any 3-variable function I0I0 I1I1 I2I2 I3I3 A B Z Example: Implement the function F(R, S, T) = R’S’ + RT F(R,S,T) = R’S’1 + RT(S+S’) = R’S’1 + R’S0 + RST + RS’T RS F(R,S,T) T T 1 0 Functions of how many input variables can be implemented by an 8-t0-1 MUX? Use an 8-t0-1 MUX to implement the function: F(X,Y,Z,T) = XY’ + Z’T 00011110

24. CMPUT 329 - Computer Organization and Architecture II24 Decoders yGeneral decoder structure yTypically n inputs, 2 n outputs y2-to-4, 3-to-8, 4-to-16, etc.

25. CMPUT 329 - Computer Organization and Architecture II25 Decoders 3-to-8 Line Decoder y 0 = a’b’c’ y 1 = a’b’c y 2 = a’bc’ y 3 = a’bc y 4 = ab’c’ y 5 = ab’c y 6 = abc’ y 7 = abc a b c

26. CMPUT 329 - Computer Organization and Architecture II26 Binary 2-to-4 decoder Note “x” (don’t care) notation.

27. CMPUT 329 - Computer Organization and Architecture II27 2-to-4-decoder logic diagram

28. CMPUT 329 - Computer Organization and Architecture II28 Negative Logic 2-to-4 Decoder zInput buffering (less load) zNAND gates (faster)

29. CMPUT 329 - Computer Organization and Architecture II29 Decoder Symbol

30. CMPUT 329 - Computer Organization and Architecture II30 Complete 74x139 Decoder

31. CMPUT 329 - Computer Organization and Architecture II31 More decoder symbols

32. CMPUT 329 - Computer Organization and Architecture II32 3-to-8 decoder

33. CMPUT 329 - Computer Organization and Architecture II33 74x138 3-to-8-decoder symbol

34. CMPUT 329 - Computer Organization and Architecture II34 Decoder Cascading 4-to-16 decoder

35. CMPUT 329 - Computer Organization and Architecture II35 More Cascading 5-to-32 decoder What is the output when the input is 01011 and the decoder is enabled? N4=0,N3=1,N2=0,N1=1,N0=1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0

36. CMPUT 329 - Computer Organization and Architecture II36 Decoder applications yMicroprocessor memory systems xselecting different banks of memory yMicroprocessor input/output systems xselecting different devices yMicroprocessor instruction decoding xenabling different functional units yMemory chips xenabling different rows of memory depending on address yLots of other applications

37. CMPUT 329 - Computer Organization and Architecture II37 Programmable Logic Arrays (PLAs) yIdea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. xn inputs AND gates have 2n inputs -- true and complement of each variable. xm outputs, driven by large OR gates Each AND gate is programmably connected to each output’s OR gate. xp AND gates (p<<2 n )

38. CMPUT 329 - Computer Organization and Architecture II38 Programmable Logic Array Structure AND Array OR Array n Input Lines m Output Lines K Word Lines PLA

39. CMPUT 329 - Computer Organization and Architecture II39 Internal Structure of a PLA R +V R R R R ABC R F0F0 R F1F1 R F2F2 R F3F3 Inputs Outputs A’B’ AC’ B BC’ AC F 0 = A’B’ + AC’

40. CMPUT 329 - Computer Organization and Architecture II40 Internal Structure of a PLA a a’ b b’ c c’ d d’ a’bd abd ab’c’ c b’c bc Word Lines F1F1 F2F2 F3F3 Outputs Inputs

41. CMPUT 329 - Computer Organization and Architecture II41 Internal Structure of a PLA A A’ Inputs B B’ C C’ AND ARRAY OR ARRAY F0F0 F1F1 F2F2 F3F3 Outputs A’B’ AC’ B BC’ AC

42. CMPUT 329 - Computer Organization and Architecture II42 Example: 4x3 PLA, 6 product terms

43. CMPUT 329 - Computer Organization and Architecture II43 Compact Representation

44. CMPUT 329 - Computer Organization and Architecture II44 PLA Electrical Design zSee Section 5.3.5 -- wired-AND logic

45. CMPUT 329 - Computer Organization and Architecture II45 Programmable Array Logic (PALs) yHow beneficial is product sharing? xNot enough to justify the extra AND array yPALs ==> fixed OR array xEach AND gate is permanently connected to a certain OR gate. yExample: PAL16L8

46. CMPUT 329 - Computer Organization and Architecture II46 Programmable Array Logic (PAL) A PAL is a special case of a PLA in which the AND array is programmable but the OR array is fixed. I1I1 I2I2 F1F1 F4F4 F5F5 F8F8 Outputs An unprogrammed PAL

47. CMPUT 329 - Computer Organization and Architecture II47 Programmable Array Logic (PAL) A PAL is a special case of a PLA in which the AND array is programmable but the OR array is fixed. I1I1 I2I2 F1F1 F4F4 F5F5 F8F8 A programmed PAL I 1 I 2 ’ + I 1 ’I 2

48. y10 primary inputs y8 outputs, with 7 ANDs per output y1 AND for 3-state enable y6 outputs available as inputs xmore inputs, at expense of outputs xtwo-pass logic, helper terms yNote inversion on outputs xoutput is complement of sum-of-products ynewer PALs have selectable inversion

49. CMPUT 329 - Computer Organization and Architecture II49 Designing with PALs yCompare number of inputs and outputs of the problem with available resources in the PAL. yWrite equations for each output using VHDL. yCompile the VHDL program, determine whether minimimized equations fit in the available AND terms. yIf they do not fit, try to modify the equations or to provide “helper” terms.

50. CMPUT 329 - Computer Organization and Architecture II50 Some Questions Is the criterion to minimize a set of functions to implement in a PAL the same that we used for the implementation with individual gates? What is the problem formulation for the implementation of a set of logic functions in a PAL?