1. 4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5

2. 4-to-1 Multiplexer Module Instantiation Logic Equation for a 4-to-1 MUX

3. 2 x 1 MUX y = a*~s + b*s

4. 4-to-1 Multiplexer z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3

5. Multiplexers z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3 0 A multiplexer is a digital switch

6. Multiplexers z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3 0 1

7. Multiplexers z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3 1 0

8. Multiplexers z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3 1

9. Creating a 4 x 1 MUX from 2 x 1 MUXs

10. -- Example 5a: 4-to-1 MUX using module instantiation library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux41 is port( c : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); z : out STD_LOGIC ); end mux41; architecture mux41 of mux41 is component mux21a port( a : in std_logic; b : in std_logic; s : in std_logic; y : out std_logic); end component; signal v, w: STD_LOGIC; begin

11. M1 : mux21a port map( a => c(0), b => c(1), s => s(0), y => v ); M2 : mux21a port map( a => c(2), b => c(3), s => s(0), y => w ); M3 : mux21a port map( a => v, b => w, s => s(1), y => z ); end mux41;

12. --Example 4a: --2-to-1 MUX using logic equations library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux21a is port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC ); end mux21a; architecture mux21a of mux21a is begin y <= (not s and a) or (s and b); end mux21a; M1 : mux21a port map( a => c(0), b => c(1), s => s(0), y => v );

13. --Example 4a: --2-to-1 MUX using logic equations library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux21a is port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC ); end mux21a; architecture mux21a of mux21a is begin y <= (not s and a) or (s and b); end mux21a; M2 : mux21a port map( a => c(2), b => c(3), s => s(0), y => w );

14. --Example 4a: --2-to-1 MUX using logic equations library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux21a is port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC ); end mux21a; architecture mux21a of mux21a is begin y <= (not s and a) or (s and b); end mux21a; M3 : mux21a port map( a => v, b => w, s => s(1), y => z );

15. Label1 : mux21a port map( a => a, b => b, s => s, y => y );

16. Aldec Active-HDL Simulation

17. 4-to-1 Multiplexer Module Instantiation Logic Equation for a 4-to-1 MUX

18. 2 x 1 MUX y = a*~s + b*s

19. v = ~s0*c0 + s0*c1 w = ~s0*c2 + s0*c3 z = ~s1*v + s1*w z = ~s1*(~s0*c0 + s0*c1) + s1*(~s0*c2 + s0*c3) z = ~s1*~s0*c0 + ~s1*s0*c1 + s1*~s0*c2 + s1*s0*c3

20. 4-to-1 Multiplexer z 4 x 1 MUX s0s1 c0 c1 c2 c3 z s1s0 0 0 c0 0 1 c1 1 0 c2 1 1 c3 z = ~s1*~s0*c0 + ~s1*s0*c1 + s1*~s0*c2 + s1*s0*c3

21. -- Example 5b: 4-to-1 MUX using logic equation library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux41b is port( c : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); z : out STD_LOGIC ); end mux41b; architecture mux41b of mux41b is begin z <= (not s(1) and not s(0) and c(0)) or (not s(1) and s(0) and c(1)) or (s(1) and not s(0) and c(2)) or (s(1) and s(0) and c(3)); end mux41b;

22. Aldec Active-HDL Simulation