2. Chapter 6 Static CMOS Circuits Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory August, 2004; Revised - June 28, 2005

3. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 2 Goals of This Chapter  In-depth discussion of CMOS logic families  Static and Dynamic  Pass-Transistor  Nonratioed and Ratioed Logic  Optimizing gate metrics  Area, Speed, Energy or Robustness  High Performance circuit-design techniques

4. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 3 Combinational Sequential Output = f(In) Output = f(In) CombinationalLogicCircuit OutIn CombinationalLogicCircuit Out In State Output = f(In, Previous In) Output = f(In, Previous In) Combinational vs. Sequential Logic

5. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 4 each gate output is connected to either V DD or V SS  At every point in time (except during the switching transients) each gate output is connected to either V DD or V SS via a low-resistance path. assume at all times the value of the Boolean function  The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods) dynamic  This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes

6. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 5 PUN and PDN are dual logic networks F(In 1,In 2,…In N ) V DD In 1 PUNPUN PDNPDN In 2 In N … … In 1 In 2 In N Static Complementary CMOS PMOS transistors only NMOS transistors only Pull-Up Network: make a connection from V DD to F when F(In 1,In 2,…In N ) = 1 Pull-Down Network: make a connection from F to GND when F(In 1,In 2,…In N ) = 0

7. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 6 Threshold Drops PDN PUN CLCLCLCL V DD  V DD 0  CLCLCLCL V DD V DD  CLCLCLCL 0  V DD CLCLCLCL SD SD S D V GS SD V DD V DD - V Tn 0 |V Tp |

8. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 7 A B AB Construction of PDN  Transistors can be thought as a switch controlled by its gate signal  NMOS switch closes when switch control input is high NMOS Transistors pass a “strong” 0 but a “weak” 1 A B Series = NAND A + B Parallel = NOR

9. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 8 Construction of PUN  PMOS switch closes when switch control input is low. PMOS Transistors pass a “strong” 0 but a “weak” 1 A B AB Series = NOR A B = A + B Parallel = NAND A + B = A B

10. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 9 Duality of PUN and PDN  PUN and PDN are dual networks  De Morgan’s theorems parallel series  A parallel connection of transistors in the PUN corresponds to a series connection of the PDN inverting  Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) N2N  Number of transistors for an N-input logic gate is 2N A + B = A B A + B = A B [!(A + B) = !A !B or !(A | B) = !A & !B] A B = A + B A B = A + B [!(A B) = !A + !B or !(A & B) = !A | !B]

11. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 10 A B A BAB ABF 001 011 101 110 Example: CMOS NAND gate V DD AB F PDN: G = A · B PUN: F = A + B Conduction to GND Conduction to V DD G(In 1, In 2, …, In N ) = F(In 1, In 2, …, In N )

12. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 11 Example: CMOS NOR gate A + B A B AB V DD ABF 001 010 100 110 AB F

13. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 12 D A BC D A B C OUT = D + A (B + C) Complex CMOS Gate Derive PUN hierarchically by identifying sub-nets

14. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 13 Cell Design: An Introduction  Standard Cells  A general purpose logic  Synthesizable  Same height but varying width  Datapath Cells  For regular, structured designs (arithmetic)  Including some wiring in the cell  Fixed height and width

15. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 14 Example of A Standard Cell Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects 2 Rails ~10 In Out V DD GND Cell height is “12 pitch” Minimum-SizeInverter

16. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 15 signals Routing channel V DD GND Standard Cell Layout Methodology – 1980s Routing channel What logic function is this?

17. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 16 M2 No Routing channels V DD GND M3 V DD GND Mirrored Cell Standard Cell Layout Methodology – 1990s

18. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 17 Contains no dimensions Represents relative positions of transistors Inverter In Out V DD GND NAND2 A Out V DD GND B Stick Diagrams

19. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 18 OAI21 Logic Graph C AB B A C i j j V DD X Xi GND AB C PUN PDN AB C X = C (A + B) Node of the circuit Transition Control

20. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 19 Two Stick Diagrams of C (A + B) ABC X V DD GND X CAB V DD GND Crossover can be eliminated by re-ordering inputs

21. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 20 j V DD X X i GND AB C ABC  For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) Consistent Euler Path  An uninterrupted diffusion strip is possible only if there exists an Euler path in the logic graph Euler path: Euler path: a path through all nodes in the graph such that each edge is visited once and only once.

22. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 21AB C D C AB B A D C D X = (A+B)(C+D) V DD X X GND AB C PUN PDN D OAI22 Logic Graph

23. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 22 BAD V DD GND C X  Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!) OAI22 Layout

24. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 23AB A  B XNOR XORAB AB AB  How many transistor in each?  Can you create the stick diagrams for the lower left circuit? XNOR/XOR Implementation

25. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 24 V GS2 = V A –V DS1 V GS1 = V B M1M1 M2M2 M3M3 M4M4 A B F= A B AB Cint D D S S 0.5  /0.25  NMOS 0.75  /0.25  PMOS weakerPUN VTC Characteristics are dependent upon the data input patterns applied to the gate (so the noise margins are also data dependent!) VTC is Data-Dependent

26. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 25 Observation I blueorange  The difference between the blue and the orange lines results from the state of internal node int between the two NMOS Devices.  The threshold voltage of M 2 is higher than M 1 due to the body effect (  ),  V SB of M 2 is not zero (when V B = 0) due to the presence of C int V Tn1 = V Tn0 and V Tn2 = V Tn0 +  (  (|2  F | + V int ) -  |2  F |)

27. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 26 Review: CMOS Inverter - Dynamic t pHL = f(R n, C L ) t pHL = 0.69 R eqn C L t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.52 C L / (W/L n k’ n V DSATn ) V DD RnRnRnRn V out V in = V DD CLCLCLCL propagation delay is determined by the time to charge and discharge the load capacitor C L

28. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 27 Review: Designing for Performance  Reduce C L  Increase W/L ratio of the transistor  the most powerful and effective performance optimization tool  watch out for self-loading!  Increase V DD  only minimal improvement in performance at the cost of increased energy dissipation  Slope engineering  Slope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values  good for performance and power consumption

29. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 28 A R eq A CLCLCLCL A RnRnRnRn A RpRpRpRp B RpRpRpRp B RnRnRnRn C int NAND RpRpRpRp A A RnRnRnRn CLCLCLCL INVERTER RpRpRpRp RpRpRpRp RnRnRnRn RnRnRnRn CLCLCLCL B A AB NOR Switch Delay Model

30. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 29 Input Pattern Effects on Delay pattern  Delay is dependent on the pattern of inputs  Low to high transition  both inputs go low 0.69 R p /2 C L  delay is 0.69 R p /2 C L since two p-resistors are on in parallel  one input goes low 0.69 R p C L  delay is 0.69 R p C L  High to low transition  both inputs go high 0.69 2R n C L  delay is 0.69 2R n C L  Adding transistors in series (without sizing) slows down the circuit CLCLCLCL A RnRnRnRn A RpRpRpRp B RpRpRpRp B RnRnRnRn C int NAND

31. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 30 Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] Input Data PatternDelay(psec) A=B=0  1 67 A=1, B=0  1 64 A= 0  1, B=1 61 A=B=1  0 45 A=1, B=1  0 80 A= 1  0, B=1 81 NMOS = 0.5  m/0.25  m, PMOS = 0.75  m/0.25  m, C L = 100 fF

32. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 31 Transistor Sizing Basic  Inverter as a reference circuit Device Transconductance (See Supplement 1) k n = k n ’(W/L) n = (µ n  ox /t ox )((W/L) n k p = k p ’(W/L) p = (µ p  ox /t ox )((W/L) p For rise time equal to fall time, k p = k n (R p = R n ) OutInVDD (W/L) p (W/L) n CLCLCLCL µ p ~ µ n /2 Because µ p ~ µ n /2 (W/L) p = 2 (W/L) n (W/L) p = 2 (W/L) n The size of PMOS must be twice as large as that of NMOS 21

33. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 32 Transistor Sizing: NAND and NOR 2222 22 1 1 4444 CLCLCLCL A RnRnRnRn A RpRpRpRp B RpRpRpRp B RnRnRnRn C int NAND RpRpRpRp RpRpRpRp RnRnRnRn RnRnRnRn CLCLCLCL B A AB NOR Symmetric Response R PUN = R PDN R p  1/(W/L) p R n  1/(W/L) n R PDN = R n + R n R PUN = R p + R p

34. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 33 Note on Transistor Sizing  By assuming R PUN = R PDN, we ignores the extra diffusion capacitance introduced by widening the transistors. velocity saturation  In DSM, even larger increases in the width are needed due to velocity saturation. 2.5 times  For 2-input NANDs, the NMOS transistors should be made 2.5 times as wide.  NAND implementation is clearly preferred over a NOR implementation  NAND implementation is clearly preferred over a NOR implementation, since a PMOS stack series is slower than an NMOS stack due to lower carrier mobility

35. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 34 1 2 22 4 4 8 8 Transistor Sizing: Complex CMOS Gate D A BC D A B C 6 6 12  Red sizing  Red sizing assuming R PUN = R PDN  Follow short path first; note PMOS for C and B,4 rather than 3 (average in pull-up chain of three = (4+4+2)/3)  Also note structure of pull-up and pull-down to minimize diffusion cap. at output (e.g., single PMOS drain connected to output)  Green  Green for symmetric response and for performance (where R p = 3R n )  Sizing rules of thumb: PMOS = 3 * NMOS

36. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 35 Fan-In Considerations DCBA D C B A CLCLCLCL C3C3C3C3 C2C2C2C2 C1C1C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

37. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 36 Notes on Fan-In Considerations V DD -V Tn to GND  While output capacitance makes full swing transition from V DD to 0, internal nodes only swing from V DD -V Tn to GND  C 1, C 2, and C 3  C 1, C 2, and C 3, each includes junction capacitance as well as the gate-to-source and gate-to-drain capacitances (turned into capacitances to ground using the Miller effect) 0.85 fF  For W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, values are on the order of 0.85 fF 3.47 fFNO  C L = 3.47 fF with NO output load (all of diffusion capacitance = intrinsic capacitance of the gate itself).  t pHL = 85 ps (simulated as 86 ps).  The simulated worst case low-to-high delay was 106 ps.

38. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 37 t p as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided. quadratic linear t pLH t p (psec) fan-in t pHL tptptptp

39. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 38 t p as a Function of Fan-Out All gates have the same drive current. t p NOR2 t p (psec) eff. fan-out t p NAND2 t p INV Slope is a function of “driving strength”

40. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 39 t p as a Function of Fan-In and Fan-Out  Fan-in:quadratic  Fan-in: quadratic due to increasing resistance and capacitance  Fan-out: two  Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO Parallel Chain Serial Chain

41. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 40 Distributed RC line M1 > M2 > M3 > … > MN output (the FET closest to the output should be the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks Fast Complex Gates: Design Technique 1  Transistor sizing  as long as fan-out capacitance dominates  Progressive sizing In N CLCLCLCL C3C3C3C3 C2C2C2C2 C1C1C1C1 In 1 In 2 In 3 M1 M2 M3 MN

42. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 41 Notes on Design Technique 1 intrinsic capacitance “self loading”  With transistor sizing, if the load capacitance is dominated by the intrinsic capacitance of the gate, widening the device only creates a “self loading” effect and the propagation delay is unaffected (and may even become worse). C 1 C 2 C L  For progressive sizing, M1 have to carry the discharge current from M2 (C 1 ), M3 (C 2 ), … MN and C L so make it the largest. C L  MN only has to discharge the current from MN (C L )(no internal capacitances).  While progressive sizing is easy in a schematic, in a real layout it may not pay off due to design-rule considerations that force the designer to push the transistors apart  increasing internal capacitance.

43. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 42 charged charged delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L discharged discharged Fast Complex Gates: Design Technique 2  Input re-ordering  when not all inputs arrive at the same time CLCLCLCL C2C2C2C2 C1C1C1C1 In 3 In 2 In 1 M1 M2 M3 critical path 1 1 01010101 charged CLCLCLCL C2C2C2C2 C1C1C1C1 In 1 In 2 In 3 M1 M2 M3 critical path 1 01010101 charged 1 Place latest arriving signal (critical path) closest to the output can result in a speed up.

44. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 43 Example: Sizing and Ordering Effects DCBA D C B A C L = 100 fF C3C3C3C3 C2C2C2C2 C1C1C1C1 3333 4 4 4 4 4 5 6 7 Progressive sizing in pull-down chain gives up to a 23% improvement. Input ordering saves 5% critical path A – 23% critical path A – 23% critical path D – 17% critical path D – 17%

45. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 44 F = ABCDEFGH Fast Complex Gates: Design Technique 3  Alternative logic structures  Reduced fan-in results in deeper logic depth Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate.

46. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 45 Notes on Design Technique 3  Reducing fan-in increases logic depth of the circuit  More stages but each stage has smaller delay simulation  Only simulation will tell which of the two alternative configurations is faster and has lower power dissipation.

47. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 46 CLCLCLCL CLCLCLCL Fast Complex Gates: Design Technique 4  Isolating fan-in from fan-out  Isolating fan-in from fan-out using buffer insertion  Optimizing the propagation delay of a gate in isolation is misguided. Reduce C L on large fan-in gates, especially for large C L, and size the inverters progressively to handle the C L more effectively

48. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 47 t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) V swing = 0.69 (3/4 (C L V swing )/ I DSATn ) Fast Complex Gates: Design Technique 5  Reducing the voltage swing  linear reduction in delay  also reduces power consumption  But the following gate is much slower! “sense amplifiers”  Or requires the use of “sense amplifiers” on the receiving end to restore the signal level (memory design)

49. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 48 Sizing Logic Paths for Speed constrained  Frequently, input capacitance of a logic path is constrained  Logic also has to drive some capacitance  Example: ALU load in an Intel’s microprocessor is 0.5pF  How do we size the ALU data path to achieve maximum speed?  We have already solved this for the inverter chain – can we generalize it for any type of logic?

50. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 49 Inverter Chain: Recap CLCLCLCLInOut 12N 1f f N-1 For given N: C i+1 /C i = C i /C i-1 = f =  (C L /C in ) N f ~ 4 N  For optimum performance, we try to keep f ~ 4, which give us the number of stages, N. logical effort  Can the same approach (logical effort) be used for any combinational circuit?

51. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 50 Delay of a Complex Logic Gate  For a complex gate, we expand the inverter chain equation  t p0  t p0 is the intrinsic delay of an inverter  f electrical effort  f is the effective fan-out (C ext /C g ) - also called the electrical effort  p  p is the ratio of the intrinsic (unloaded) delay of the complex gate and a simple inverter (a function of the gate topology and layout style)  glogical effort  g is the logical effort

52. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 51 Notes on Delay of a Logic Gate Gate delay: D = h + p Effort delay Intrinsic delay Effort delay: h = g f Logical Effort Electrical Effort (effective fan-out)  Logical effort first defined by Sutherland and Sproull in 1999.  In a simpler format, = C out /C in

53. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 52 Intrinsic Delay Term, p  The more involved the structure of the complex gate, the higher the intrinsic delay compared to an inverter Ignoring second order effects such as internal node capacitances Gate Type p Inverter1 n-input NANDn n-input NORn n-way mux2n2n XOR, XNORn 2 n-1

54. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 53 Logical Effort Term, g g  Logical effort of a gate, g, presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current  g  g represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response Gate Type g (for 1 to 4 input gates) 1234 Inverter1 NAND4/35/3(n+2)/3 NOR5/37/3(2n+1)/3 Mux222 XOR412

55. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 54 Notes on Logical Effort  Inverter  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates  Logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver same output current)  Logical effort is a function of topology, independent of sizing  Logical effort increases with the gate complexity  Electrical effort (Effective fanout) is a function of load/gate size

56. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 55 A + B A B AB A A A 2 1 C unit = 3 22 2 2 C unit = 4 4 4 11 C unit = 5 Example of Logical Effort C unit  Assuming a PMOS/NMOS ratio of 2, the input capacitance of a minimum-sized inverter is three times the gate capacitance of a minimum-sized NMOS (C unit ) A B A B AB

57. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 56 Delay as a Function of Fan-Out  The slope of the line is the logical effort of the gate  The y-axis intercept is the intrinsic delay  Can adjust the delay by adjusting the effective fan-out (by sizing) or by choosing a gate with a different logical effort normalized delay fan-out f NAND2: g=4/3, p = 2 INV: g=1, p=1 intrinsic delay effort delay Gate Effort: h = fg

58. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 57 1 a b c CLCLCLCL 5 Path Delay: Complex Logic Gate Network  Total path delay through a combinational logic block t p =  t p,j = t p0  (p j + (f j g j )/  )  So, the minimum delay through the path determines that each stage should bear the same gate effort f 1 g 1 = f 2 g 2 =... = f N g N  Consider optimizing the delay through the logic network how do we determine a, b, and c sizes?

59. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 58 Path Delay Equation Derivation  The path logical effort, G =  g i  And the path effective fan-out (path electrical effort) is F = C L /g 1  The branching effort accounts for fan-out to other gates in the network b = (C on-path + C off-path )/C on-path  The path branching effort is then B =  b i H = GFB  The total path effort is then H = GFB  So, the minimum delay through the path isN D = t p0 (  p j + (N  H)/  )

60. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 59 Example: Complex Logic Gates  For gate i in the chain, its size is determined by  For this network  F = C L /C g1 = 5  G = 1 x 5/3 x 5/3 x 1 = 25/9  B = 1  B = 1 (no branching)  H = GFB = 125/9  H = 1.93  H = GFB = 125/9, so the optimal stage effort is  H = 1.93 f 1 =1.93, f 2 =1.93 x 3/5 = 1.16, f 3 = 1.16, f 4 = 1.93  Fan-out factors are f 1 =1.93, f 2 =1.93 x 3/5 = 1.16, f 3 = 1.16, f 4 = 1.93  So the gate sizes are a = f 1 g 1 /g 2 = 1.16, b = f 1 f 2 g 1 /g 3 = 1.34 and c = f 1 f 2 f 3 g 1 /g 4 = 2.60 4 j=1 i -1 s i = (g 1 s 1 )/g i  (f j /b j ) 1 a b c CLCLCLCL 5

61. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 60 Example – 8-input AND

62. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 61 Summary: Method of Logical Effort  Compute the path effort: F = GBH  Find the best number of stages N ~ log 4 F  Compute the stage effort f = F 1/N  Sketch the path with this number of stages  Work either from either end, find sizes: C in = C out *g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

63. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 62 Summary: Key Definitions Sutherland,SproullHarris

64. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 63 Ratioed Logic  N  N transistors + Load  V OH = V DD  V OL = R PDN / (R PDN + R L )   Asymmetrical Response  Static Power consumption P low   t pL = 0.69 R L C L Goal: To Reduce the number of devices over complementary CMOS

65. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 64 Ratioed Logic: Active Loads

66. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 65 Pseudo NMOS NAND and NOR D C B A CLCLCLCL F NAND DCBA CLCLCLCL F NOR   Psedo-NMOS is useful when area is most important  Reduce transistor counts  Used occasionally for large fan-in gates

67. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 66 Pseudo-NMOS Inverter Characteristics  Assumptions:  NMOS resides in linear mode  V OL is small relative to the gate drive (V DD -V T ))

68. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 67 Pseudo-NMOS Inverter VTC 0.00.51.01.52.02.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 W/L p = 4 W/L p = 2 W/L p = 1 W/L p = 0.25 W/L p = 0.5 V out (V) V in (V) Size V OL (V) (V) P stat (µW) t pLH (ps)40.69356414 20.27329856 10.133160123 0.50.06480268 0.250.03141569 NMOS size = 0.5 µm/0.25 µm Larger pull-up device not only improves performance (delay) but also increases power dissipation and lowers noise margins by increasing V OL

69. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 68  M1 >> M2   The idea is to reduce static power consump- tion by adjusting the load  Load M2 when there are not too many inputs (A, B, C, or D) active  Switch to Load M1 when all inputs are active (thus require high amount of current to drive) Improved Loads: Adaptive Load Enable

70. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 69 Improved Loads: DCVSL

71. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 70 DCVSL Example

72. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 71 DCVSL Characteristics  Dual Rail Logic  Each input is provided in complementary format and each gate produces complementary output  Increasing complexity  Rail-to-Rail Swing  No static power dissipation  Sizing of the PMOS relative to PDN is critical to functionality, not just performance  PDNs must be strong enough to bring outputs below V DD - |V Tp |

73. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 72 DCVSL Transient Response 00.20.40.60.81.0 -0.5 0.5 1.5 2.5 Time [ns] V o l t a g e [V] A B A,B A,B Transient Response of a 2-input AND/NAND gate. How does it look like? t in->out = 197 ps t in->out = 321 ps

74. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 73 AB XY X = Y if A and B XY A B X = Y if A or B NMOS Transistors in Series/Parallel  Primary inputs drive both gate and source/drain terminals  NMOS switch closes when the gate input is high Remember - NMOS transistors pass a strong 0 but a weak 1

75. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 74 PMOS Transistors in Series/Parallel  Primary inputs drive both gate and source/drain terminals  PMOS switch closes when the gate input is low Remember - PMOS transistors pass a strong 1 but a weak 0 X = Y if A and B = A + B X = Y if A or B = A  B AB XY XY A B

76. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 75 ABF B 0 A 0BB F Pass Transistor (PT) Logic static  Gate is static – a low-impedance path exists to both supply rails under all circumstances N2N  N transistors instead of 2N No static power consumption  No static power consumption Ratioless  Ratioless Bidirectional  Bidirectional (versus undirectional) = A  B

77. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 76 A 0BB F= A  B 0.5/0.25 1.5/0.25 B = V DD, A = 0  V DD A = V DD, B = 0  V DD A = B = 0  V DD V out, (V) V in, (V) l Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion) VTC of PT AND Gate

78. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 77 Complementary PT Logic (CPL) BAA B PT Network F F B A A B Inverse F F A A B F=A+B BBBOR/NOR F=A+B A A B F=A·B BBBAND/NAND F=A·B F=A  B A A A ABBXOR/XNOR

79. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 78 CPL Properties  Differential,  Differential, so complementary data inputs and outputs are always available (don’t need extra inverters)  Static  Static, since the output defining nodes are always tied to V DD or GND through a low resistance path modular  Design is modular; all gates use the same topology, only the inputs are permuted. adders  Simple XOR makes it attractive for structures like adders  Fast!  Fast! (assuming number of transistors in series is small) routing overhead  Additional routing overhead for complementary signals  Still have static power dissipation problems

80. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 79 NMOS-Only PT Driving an Inverter M 2  Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND) body effect  Notice V Tn increases of pass transistor due to body effect (V SB ) V x does not pull up to V DD, but V DD – V Tn V GS In = V DD A = V DD VxVxVxVx M1M1M1M1 M2M2M2M2 B SD Out

81. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 80 Voltage Swing of PT Driving an Inverter  Body effectX  Body effect – large V SB at X - when pulling high (B is tied to GND and S charged up close to V DD )  So the voltage drop is even worse V x = V DD - (V Tn0 +  (  (|2  f | + V x ) -  |2  f |)) Time (ns) Voltage (V) In Out X = 1.8V In = 0  V DD V DD X Out 0.5/0.25 1.5/0.25 D S B

82. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 81 Cascaded NMOS-Only PTs B = V DD Out M1M1 y M2M2 A = V DD C = V DD x GS GS x M1M1 B = V DD Outy M2M2 C = V DD A = V DD = V DD - V Tn1 Swing on y = V DD - V Tn1 - V Tn2 Swing on y = V DD - V Tn1 never  Pass transistor gates should never be cascaded as on the left static power dissipationreduced noise margins  Logic on the right suffers from static power dissipation and reduced noise margins

83. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 82 M1M1 M2M2 A MnMn xBOut Solution 1: Level Restorer ratioed  For correct operation M r must be sized correctly (ratioed) x no static power consumption  Full swing on x (due to Level Restorer) so no static power consumption by inverter  No static backward current path A  No static backward current path through Level Restorer and PT since Restorer is only active when A is high Level Restorer MrMr ABXOut MrMrMrMr 0 0  V DD 0V DDOFF 0  V DD V DD 0ON

84. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 83 Transient Level Restorer Circuit Response Voltage (V) Time (ps) W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.25/0.25 W/L r =1.0/0.25 node x never goes below V M of inverter so output never switches  Restorer has speed and power impacts: xslowing down the gate  Increases the capacitance at x, slowing down the gate t r t f  Increases t r (but decreases t f ) W/L n =0.50/0.25, W/L 1 =0.50/0.25, W/L 2 =1.50/0.25

85. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 84 Notes on Level Restorer stronger X  Pull down must be stronger than restorer (pull up) to switch node X X the inverter never switches!  If resistance of restorer transistor is too small (too wide transistor) it is impossible to bring the voltage at node X below the switching threshold of the inverter, and the inverter never switches! M r  Sizing of M r is critical for DC functionality, not just performance!! Dynamic Logic  It belongs to Dynamic Logic Family

86. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 85 Solution 2: Multiple V T Transistors most  Technology solution: Use (near) zero V T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) Out In 2 = 0V In 1 = 2.5V A = 2.5V B = 0V low V T transistors sneak path on off but leaking Watch out for subthreshold current flowing through PTs

87. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 86 Solution 3: Transmission Gates (TGs)  Full swingbidirectional  Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1 A B CC B C = V DD C = GND A = V DD B C = V DD C = GND A = GND  Most widely used solution A B CC

88. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 87 Resistance of TG V out (V) Resistance (k  ) RpRpRpRp RnRnRnRn R eq RpRpRpRp RnRnRnRn 2.5V 0V 2.5V V out W/L n =0.50/0.25 W/L p =0.50/0.25 series resistance  TG is not an ideal switch - series resistance  R eq constant resistance  R eq is relatively constant ( about 8kohms in this case), so can assume has a constant resistance R eq = R p || R n R eq = R p || R n

89. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 88SS S In 2 In 1 F F = !(In 1  S + In 2  S) GND V DD In 1 In 2 S S SSF TG Multiplexer

90. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 89 off B A A  B Transmission Gate XOR  Fnot dynamic  F always has a connection to V DD or GND - not dynamic  No voltage drop 6 Transistors

91. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 90 Transmission Gate XOR B A F = A‘ V DD (B) 0 (B’) B= 1an inverter FB = 1A’  When B = 1, the circuit behaves as if it is an inverter, hence F(B = 1) = A’ off 1

92. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 91 Transmission Gate XOR B= 0 FB = 0A  When B = 0, the circuit acts as a transmission gate, hence F(B = 0) = A (TG ensures no voltage drop) B A F = A when A = 0 weak 0 weak 1 when A = 1 V DD (B’) 0 (B) on 0

93. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 92 Transmission Gate XOR B A A‘ B + A B’  Combine the results using Shannon’s expansion theorem, F = B·F(B = 1) + B’·F(B = 0) = A’B+AB’ = A  B

94. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 93 TG Full Adder Sum C out A B C in 16 Transistors, no more than 2 PTs in series 16 Transistors, no more than 2 PTs in series Full swing Full swing Similar delay for Sum and Carry Similar delay for Sum and Carry

95. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 94 Differential TG Logic (DPL) A A BBB F=A  B XOR/XNOR AABBAAB AND/NAND F=AB F=AB A A BBABA GND V DD B

96. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 95 Delay of a TG Chain CCCC VNVNVNVN V1V1V1V1 ViViViVi V i+1 50505050 V in N  Delay of the RC chain (N TG’s in series) is t p (V n ) = 0.69  kCR eq = 0.69 CR eq (N(N+1))/2  0.35 CR eq N 2 R eq V in CCCC V1V1V1V1 ViViViVi V i+1 VNVNVNVN

97. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 96 Notes on TG Chain Delay quadratically in N  Delay grows quadratically in N (in this case in the number of TGs in series) and increases rapidly with the number of switches in the chain.  E.g., for 16 cascaded minimum-sized TG’s, each with an R eq of 8kohms.  The node capacitance is the sum of the capacitances of two NMOS and PMOS devices (junctions and drains).  Capacitance values is approx. 3.6 fF for low to high transitions.  The delay through the chain is  t p = 0.69 CR eq (N(N+1))/2 = 0.69 x 3.6fF x 8kΩ x (16x17)/2 = 2.7ns

98. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 97 M  Delay of buffered chain (M TG’s between buffer) t p = 0.69  N/M CR eq (M(M+1))/2  + (N/M - 1) t pbuf M opt = 1.7  (t pbuf /CR eq )  3 or 4 TG Delay Optimization  Can speed it up by inserting buffers every M switches V in VNVNVNVN M C 505050C C 505050C CC

99. B.Supmonchai 2102-545 Digital ICs Static CMOS Circuits 98 Notes on Delay Optimization linear in N  Buffered chain is now linear in N MM should be small  Quadratic in M but M should be small  This buffer insertion technique works to speed up the delay down long wires as well.  Consider 16TG chain example. Buffers = inverters (making sure correct polarity is output).  For 0.5micron/0.25micron NMOSs and PMOSs in the TGs, 154 ps  simulated delay with 2TG per buffer is 154 ps, 154ps164ps  for 3TGs is 154ps, and for 4TG is 164ps.  The insertion of buffering inverters reduces the delay by a factor of almost 2.