1. ECE 15B Computer Organization Spring 2011 Dmitri Strukov Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy,

2. Agenda Instruction formats Addressing modes Advanced concepts ECE 15B Spring 2011

3. Instruction formats ECE 15B Spring 2011

4. Simple datapath picture Let’s add more details on this figure to see why instruction decoding could be simple and to see what is happening with for different instructions ECE 15B Spring 2011

5. Below the Program lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Assembly Language Program (e.g.,MIPS) Machine Language Program (MIPS) Hardware Architecture Description (e.g., block diagrams) Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Logic Circuit Description (Circuit Schematic Diagrams) Architecture Implementation

6. Assembly instruction ECE 15B Spring 2011 0000 1001 1100 0110 1010 1111 0101 1000 Binary code lw $t0, 0($2) always 32 bits One assembly instruction = 32 bit vector Macro or pseudo instruction  > one line of code Examples: shift and rotate from Quiz 1 rol $a0, $a1, $a2 subu $t0, $0, $a2 srlv $t0, $a1, $t0 sllv $a0, $a1, $a2 or $a0, $a0, $t0 One to one mapping

7. Datapath With Control ECE 15B Spring 2011

8. Instruction formats ECE 15B Spring 2011 oprsrtrdshamtfunct 6 bits 5 bits R-format: oprsrtconstant or address 6 bits5 bits 16 bits opaddress 6 bits 26 bits I-format: J-format:

9. R-format Example add $t0, $s1, $s2 special$s1$s2$t00add 017188032 00000010001100100100000000100000 00000010001100100100000000100000 2 = 02324020 16 oprsrtrdshamtfunct 6 bits 5 bits note the order! (green card) ECE 15B Spring 2011

10. R-Type Instruction ECE 15B Spring 2011

11. Instruction formats ECE 15B Spring 2011 oprsrtrdshamtfunct 6 bits 5 bits R-format: oprsrtconstant or address 6 bits5 bits 16 bits opaddress 6 bits 26 bits I-format: J-format:

12. Load Instruction ECE 15B Spring 2011

13. Instruction formats ECE 15B Spring 2011 oprsrtrdshamtfunct 6 bits 5 bits R-format: oprsrtconstant or address 6 bits5 bits 16 bits opaddress 6 bits 26 bits I-format: J-format:

14. Target Addressing Example Loop code from earlier example – Assume Loop at location 80000 Loop: sll $t1, $s3, 2 800000019940 add $t1, $t1, $s6 8000409229032 lw $t0, 0($t1) 8000835980 bne $t0, $s5, Exit 8001258212 addi $s3, $s3, 1 80016819 1 j Loop 80020220000 Exit: … 80024 ECE 15B Spring 2011

15. Branch-on-Equal Instruction ECE 15B Spring 2011

16. MIPS PC-relative or branch addressing Branch instructions specify – Opcode, two registers, target address Most branch targets are near branch – Forward or backward oprsrtconstant or address 6 bits5 bits 16 bits PC-relative addressing Target address = PC + offset × 4 PC already incremented by 4 by this time ECE 15B Spring 2011

17. Instruction formats ECE 15B Spring 2011 oprsrtrdshamtfunct 6 bits 5 bits R-format: oprsrtconstant or address 6 bits5 bits 16 bits opaddress 6 bits 26 bits I-format: J-format:

18. Target Addressing Example Loop code from earlier example – Assume Loop at location 80000 Loop: sll $t1, $s3, 2 800000019940 add $t1, $t1, $s6 8000409229032 lw $t0, 0($t1) 8000835980 bne $t0, $s5, Exit 8001258212 addi $s3, $s3, 1 80016819 1 j Loop 80020220000 Exit: … 80024 ECE 15B Spring 2011

19. Datapath With Jumps Added ECE 15B Spring 2011

20. Pseudodirect or Jump Addressing Jump ( j and jal ) targets could be anywhere in text segment – Encode full address in instruction opaddress 6 bits 26 bits (Pseudo)Direct jump addressing Target address = PC 31…28 : (address × 4) ECE 15B Spring 2011

21. Implementing Jumps Jump uses word address Update PC with concatenation of – Top 4 bits of old PC – 26-bit jump address – 00 Need an extra control signal decoded from opcode 2address 31:2625:0 Jump ECE 15B Spring 2011

22. Branching Far Away If branch target is too far to encode with 16- bit offset, assembler rewrites the code Example beq $s0,$s1, L1 ↓ bne $s0,$s1, L2 j L1 L2:… ECE 15B Spring 2011

23. Note on the PC incrementing Technical term for auto-incrementation of PC is “delayed branch” By default in SPIM “delayed branch” is not checked. To see you SPIM settings look at simulator  settings You can also check it by loading code to SPIM to check main : bne $s0, $s0, main ECE 15B Spring 2011

24. Loading constant values to registers Any immediate is 16 bit To load 32 bits constant one can use addi, sll + addior better way to use lui rd, const(load upper immediate) ECE 15B Spring 2011

25. Specific Addressing Mode in MIPS ECE 15B Spring 2011

26. Various specific addressing modes in other ISAs Absolute address Immediate data Inherent address Register direct Register indirect Base register Register indirect with index register Register indirect with index register and displacement Register indirect with index register scaled Absolute address with index register Memory indirect Program counter relative ECE 15B Spring 2011

27. Example: Basic x86 Addressing Modes Two operands per instruction Source/dest operandSecond source operand Register Immediate RegisterMemory Register MemoryImmediate Memory addressing modes Address in register Address = R base + displacement Address = R base + 2 scale × R index (scale = 0, 1, 2, or 3) Address = R base + 2 scale × R index + displacement ECE 15B Spring 2011

28. Advanced Topics: Code density examples ECE 15B Spring 2011

29. Recent study (2009) ECE 15B Spring 2011

30. Code density examples ECE 15B Spring 2011

31. Advanced topics: Pipelining ECE 15B Spring 2011

32. Datapath With Control ECE 15B Spring 2011

33. Pipelining Analogy Pipelined laundry: overlapping execution – Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non-stop: Speedup = 2n/0.5n + 1.5 ≈ 4 = number of stages ECE 15B Spring 2011

34. Pipeline registers Need registers between stages – To hold information produced in previous cycle ECE 15B Spring 2011

35. Multi-Cycle Pipeline Diagram Traditional form ECE 15B Spring 2011

36. Advanced topics: Cache design basics ECE 15B Spring 2011

37. Datapath With Control ECE 15B Spring 2011

38. Principle of Locality Programs access a small proportion of their address space at any time Temporal locality – Items accessed recently are likely to be accessed again soon – e.g., instructions in a loop, induction variables Spatial locality – Items near those accessed recently are likely to be accessed soon – E.g., sequential instruction access, array data ECE 15B Spring 2011

39. Taking Advantage of Locality Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory – Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory – Cache memory attached to CPU ECE 15B Spring 2011

40. Direct Mapped Cache Location determined by address Direct mapped: only one choice – (Block address) modulo (#Blocks in cache) #Blocks is a power of 2 Use low-order address bits ECE 15B Spring 2011

41. Tags and Valid Bits How do we know which particular block is stored in a cache location? – Store block address as well as the data – Actually, only need the high-order bits – Called the tag What if there is no data in a location? – Valid bit: 1 = present, 0 = not present – Initially 0 ECE 15B Spring 2011

42. Example: Direct mapped cache ECE 15B Spring 2011