1. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction University of California MICRO ’03 Presented by Jinho Seol

2. Motivation By 2015 processors will consume 300W Existing CMP designs use only homogeneous cores Applications with high ILP can be exploited on wider cores but applications with low ILP use less power on narrower cores with little loss in performance

3. Main Idea Single-ISA heterogeneous multi-core architecture – A mechanism to reduce power dissipation Key idea – Choose the most power efficient processor under some performance constraints  Power efficiency

4. Architecture Private L1 caches and a common L2 cache Assumption Only one application runs at a time on only one core Unused cores are completely powered down Switching timing OS time slice intervals Entire application

5. Modeling of CPU Cores Roughly modeled after cores of EV4(Alpha 21064), EV5(Alpha 21164), EV6(Alpha 21264) and EV8- (Alpha 21464) Assumption – 0.10 micron technology EV8- – Single-threaded version of EV8 – Subtracting out L2 cache

6. Modeling of Power Peak power – Data obtained from data sheets – EV8- data is estimated Core-area – Estimated using CACTI Typical power – Assumed from Intel processors – EV4 and EV5 is extrapolated

7. Variation in Power & Performance Benchmark, applu Relative performance of the cores varies between phases.

8. Oracle based on energy metric Oracle chooses the core that has the lowest energy consumption, given the constraint that performance has always to be maintained within 10% of the EV8- core

9. Oracle based on energy-delay metric Oracle chooses the core that has the lowest energy–delay product. – Assumption that energy and response time have equal importance.

10. Realistic Dynamic Switching Heuristics Assumption – An ability to track both the accumulated performance and energy over a past interval Heuristics – Neighbor One of the 2 neighboring cores in the performance continuum is randomly selected for sampling. – Neighbor-global Similar to neighbor, except selecting the accumulated energy-delay product. – Random Randomly-chosen core is sampled. – All All cores are sampled.

11. Conclusion Realistic dynamic switching algorithms show a decrease in energy and energy- delay with a small decrease in performance Single ISA heterogeneous multi-core processors may be a way to decrease power dissipation