1. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 1 Commissioning/Status Pile-Up System

2. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 2 PU System overview

3. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 3 PU System overview Comparator thresholds Beetle+Optical Tx timing Binary link synchronisation BXid labelling BXid offset w.r.t. BXrst Peak height threshold

4. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 4 Hybrid Problem with thermal behaviour –“re-invented” bi-metal Carbon fiber reinforcement solution 4 modules mounted on velo halves Tested in assembly lab –Analog, digital and thermal Waiting for VELO installation in IP8 –End of October

5. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 5 Optical station Production done (8+2 spare) Tests –Optical links BERR ok –VHDL minor update needed –Time alignment tests ongoing Partial optical station (1/2) installation second half November –4 optical boards –4 transition boards –2 VELO control boards Optical station needed for hybrid commissioning 128 LVDS Data 80 Mb/s LVDS receivers GOL Data sync Event multiplexing BCID labeling LHC clock Qpll-DeJitter Clocktree Parallel Optical transmitter JTAG (lab only) I2C, POR, BCIDrst Optical Tx Board GOL Actel APA300 Power VELO ctrl brd 12

6. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 6 VEPROB Production done Implement RAW data format Vertex finder algorithm tests matches VHDL simulation –Input from pattern memories Test L0 buffer ongoing Testing DAQ path –Using simple DAQ optical TELL1 –Analyze MEP (only error banks) Optical Ribbon Orc Card Optical Ribbon Orc Card Channel Sync Ethernet CCPC Glue Card Optical transmitters JTAG Xv2pro100 Vertex Finder Opt in. TTCRq Monitor & control VEPROB MGT L0 buffer MGT TFC ECS Output board DAQ (TELL1)

7. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 7 Output Board Suffering from manpower problems (hybrid and non-LHCb projects) –Layout two more weeks needed Aim for production done before Christmas Components ordered VHDL code not complete –Focus on merging data streams from VEPROB –Histogramming implementation will be finished at a later stage

8. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 8 Cabling 256+16 Binary links –Pulling finished September 2007 –To be connected / tested Optical ribbons –To be tested –Patch cords and breakouts in house Control cables –Pulled together with VELO Analog links –Tested LV cables –Together with VELO –Finished half november Will be tested in VELO slice test

9. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 9 Commissioning Hardware available for commissioning @ip8, half november –Vertex tank 4 silicon modules 12 digital (passive) repeater 4 analog repeaters –Optical station 4 Optical TX Boards 4 transition boards Backplane 2 Velo control boards –Processor crate 2/3 VEPROBs 4 analog TELL1s 1 optical TELL1

10. L0 Workshop 17/10/2007 Wilco Vink / Martin van Beuzekom Leo Wiggers / Sander Mos 10 Commissioning steps Power check –Crates –LV hybrids ECS check –Programming hybrids –Optical Boards register access –CCPC boot/Lbus/i2c/JTAG Gb Ethernet –Check MEP reception (test mode TELL1) Connectivity test –Optical link test Optical Boards -> VEPROBs –Optical link test DAQ path (TELL1) –Binary (copper) links –Untangle link swaps Tune timing –Sample timing Optical Boards Beetle testpulse needed –Event labeling Beetle threshold scans Check algorithm –Pattern from VEPROB memory –With Beetle testpulse Test with L0DU (output board) Nov 2007 Dec 2007 2008