1. 1)A 13 bit address 8 bit parallelism processor has a 1KB EPROM at address 4K and it is sure that no address in the 5K-6K is used. What is the simplest CS of the EPROM? 2)If a processor uses a rectangular clock whose frequency is 2 GHz and the duty cycle of the clock is 33% how long is each one of the two half periods? 3)A full associative cache (without validity and other status bits) contains 64 slots and its lines are 8 bytes. If the size of the cache in bits is 4928, how many are the address bits of the processor? 4)The TLB (set associative – 4 ways) of a paged 32 bit address processor (4KB pages) has 32 slots: what is the size in bits of the TLB?

2. 1)A 13 bit address 8 bit parallelism processor has a 1KB EPROM at address 4K and it is sure that no address in the 5K-6K is used. What is the simplest CS of the EPROM? 13 bit address => A12…A00 => 8K address space CS4K = A12 !A11 !A10 but the CS5K = A12 !A11 !A10 is not used so CS4K = A12 !A11 !A10 or A12 !A11 !A10 = A12 !A11 (!A10 or A10) = A12 !A11 1 = A12 !A11 And in fact this would correspond to a 2K device in a 8K address space => only 4 devices! 2)If a processor uses a rectangular clock whose period of 2 GHz and the duty cycle of the clock is 30% how long is each one of the two half periods? 2GHz => 500psec 1/3 2/3 166,6 psec 333,3 psec

3. 3)A full associative cache (without validity and other status bits) contains 64 slots and its lines are 8 bytes. If the size of the cache in bits is 4928, how many are the address bits of the processor? 64 slots x 8bytes/line x 8bits/byte = 4096 bit for the lines 4928 – 4096 = 832 for the tags 64 slots => 832 / 64 = 13 bit/tag 13 bit/tag + 3 bits/line = 16 bit address 4)The TLB (set associative – 4 ways) of a paged 32 bit address processor (4KB pages) has 32 slots: what is the size in bits of the TLB (not considering validity and status bits)? 2x[ 32 slots x 4 ways/slots x (32 address bit -12bit address in page)] = 2 x [32 x4 x20] = 5120 bit Why x2 ? Because TLB tag and data have the same size (the TLB transforms the high part of the virtual address into the high part of the physical address. The in page address is the same)