1. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Topics Buses and networks-on-chips. Networks-on-chips. Data paths. Subsystems as IP.

2. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus-based systems A bus is a common connection: box1box2box3 ctrl data

3. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus circuits Cannot support full connectivity between all data path elements—must choose number of transfers per cycle allowed. A bus circuit is a specialized multiplexer circuit. Two major choices: pseudo-nMOS, precharged.

4. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Pseudo-nMOS bus circuit

5. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Precharged bus circuit

6. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Three-state bus

7. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Asynchronous timing constraints Must satisfy setup, hold times. adrs Setup time Hold time

8. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus system design Requirements: –Imposed by the other side of the system. Constraints: –Imposed by this side of the system. ab requirements constraints

9. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf ba Views of the bus Hardware: DQDQ Combinational logic

10. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Views of bus system, cont’d. Timing diagram: ba DQDQ Combinational logic x y xy

11. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus protocols Basic transaction: –four-cycle handshake. a b

12. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Handshake machine Each side is an FSM (possibly asynchronous): ab 01 Go ack enq 01 ack

13. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Basic protocols Handshake transmits data:

14. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Box 1 logic

15. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Box 2 logic

16. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus timing t d1 = d stable t d2 = d not stable t c1 = c rises t c2 = c falls t ack1 = ack rises t 1 = t c1 - t d1 >= t r t 2 = t ack1 - t c1 >= t h t 3 = t c2 - t ack1 >= t h

17. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Busses and systems Microprocessor systems often have several busses running at different rates: CPU bridge mem I/O High-speed Low-speed

18. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Basic signals in a bus

19. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus characteristics Physical –Connector size, etc. Electrical –Voltages, currents, timing. Protocol –Sequence of events.

20. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Advanced transactions Multi-cycle transfers: –Several values on one handshake. –May use implicit addressing.

21. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf PCI bus Used for box-level system interconnect. Two versions: –33 MHz. –66 MHz. Supports advanced transactions.

22. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf PCI bus read

23. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Multi-rate systems Logic blocks running at different clock rates may communicate: –Multi-chip. –Single-chip. »Slow bus connects to fast logic. Logic 1Logic 2 100 MHz33 MHz

24. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Metastability Registers capturing transitioning signals may take an arbitrarily long time to settle.

25. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Resynchronization Use cascaded registers to minimize the chance of using a metastable value. DQDQ ddout 

26. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Networks-on-chips NoC is an on-chip interconnection network. –Bus is simplest case. –Many NoCs have multiple stages. Packet-based NoCs: –Nodes connected by links. –Packet may be divided into flits (flits are always of equal size, packets may not be).

27. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus electrical model core i Length 1

28. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bus delay Major components of delay: –Drivers. –Bus backbone. –Sink capacitive loads. Delay formula:

29. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Crossbar Crossbar allows any combination of connections. Allows arbitrary multicasting.

30. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Switch-based crossbar

31. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Mux-based crossbar 2-to-1 mux cellMux tree

32. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Crossbar delay Switch-based crossbar dominated by buffered transmission line: Multiplexer-based crossbar delay:

33. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Network comparison TypeDelay BusO(N 2 ) Switch-based crossbar O(sqrt(N)) Mux-based crossbar O(log N)

34. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data paths A data path is a logical and a physical structure: –bitwise logical organization; –bitwise physical design. Datapath often has ALU, registers, some other function units. Data is generally passed via busses.

35. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data path logical organization Register file shifter memory constant addresses Shift control ALU op carry out

36. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Register file porting Register file is an SRAM. Additional ports add area, increase access time. But additional ports also reduce number of cycles required for an operation.

37. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Operand fetch from register file + 1 port First cycle Second cycle Third cycle 2 ports First cycle Second cycle 3 ports First cycle

38. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Register file tradeoffs SRAM delay grows approximately linearly in number of ports. Driver area grows considerably with added ports. At least two ports makes sense for data path through put.

39. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data path clocking Major signals: –  1 –  2 –precharge s  1 –adrs s  2 –data v  2

40. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data path timing Register file shifter s  1 s  2 11 22

41. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Typical data path structure Slice includes one bit of function units, connected by busses: registersshiftALU bus

42. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Bit-slice structure Many arithmetic and logical functions can be defined recursively on bits of word. A bit-slice is a one-bit (or n-bit) segment of an operation of minimum size to ensure regularity. Regular logical structure allows regular physical structure.

43. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Abutting and pitch-matching Cells in bit-slice may be abutted together—requires matching positions on terminals. Pitch-matching is designing cells to ensure that pins are at proper positions for abutting.

44. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data path floorplan muxlatch muxconstant Register file shifter ALU

45. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Data path color plan cell VDD VSS result Shifter input Register file control

46. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Subsystems as IP Standards for subsystems are more complex: –More variations. –More parameters. Open Core Protocol (OCP) defines socket for plug-and-play operation. SPIRIT defines standard documentation for subsystem IP.

47. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Wishbone standard Basic unit is master-slave interface. –Defines handshake. Interface defines CLK, ADRS, DATA, WE, STB, ACK, CYC, RST. Three types of bus transfers: single read/write, block read/write, read/modify/write.

48. Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Functional verification Particularly important for soft IP, but performed even for hard IP. Compare design module against known good design. QIP metric standard defines verification standards. golden reference IP module - input vectors