1. Electrocardiogram (ECG) application operation Performed By: Ran Geler Mor Levy Instructor:Moshe Porian Project Duration: 2 Semesters Spring 2012 Characterization Presentation

2. Contents Intro Project Overview Project Goals Top Architecture Data Flow Features GUI Schedule

3. Intro The heart is a muscular organ that beats in rhythm to pump blood through the body By analyzing the heart behavior and especially the electrical impulses we can help identify heart diseases and special circumstance that require close monitoring

4. Medical Terms ECG Lead ◦ Bipolar leads ◦ Unipolar leads ◦ Precordial Leads

5. Project Overview

6. Project Goals Portable ECG device based on FPGA while considering: ◦ Performance / Cost reduction Integrating Multi Platforms elements ◦ ECG DB with FPGA Interactive GUI

7. Top Architecture

8. Data Flow FPGA The host send a request ADS1298R ECG DB Host

9. Data Flow FPGA The FPGA initialize data mining ADS1298R ECG DB Host

10. Data Flow FPGA ADS1298R ECG DB The DB sample the electrodes and send the data back to the FPGA Host

11. Data Flow FPGA ADS1298R ECG DB The FPGA returns the RAW -data to the pc for analyze and present results Host

12. Texas Instruments ADS1928R Main features: Low-Power 8-Channel (Electrodes), 24-Bit Analog Biopotential Measurements Data rate: 250SPS to 32kSPS Eight Low Noise PGAs Eight High Resolution ADCs

13. Texas Instruments ADS1928R Main features – cont: 24 output bits of data per channel in binary twos complement SPI compatible Pace detection

14. Texas Instruments ADS1928R

15. DB Issues Acquisition of the Eval-kit Future acquisitions of probes and electrodes Connection of the DB to the FPGA

16. GUI - Features Scope FFT Pace detect User Data base Debugging abilities

17. GUI – Main window GUI – Main window

18. GUI – Analyser GUI – Analyser

19. GUI – Debugger GUI – Debugger

20. Schedule – Semester A Acquisition of the Ti ADS1928R DB Full System characterization Define the interface between the user, GUI, FPGA and the DB card Detail Design of the FPGA and VHDL implementation Building simulation environment Semi-semester Presentation 2w 4w 1w

21. Schedule – Semester A Cont.. Further simulation and final code release Synthesis and P&R by Quartus Semester A -Final Presentation 4w 3w 1w

22. Schedule – Semester B Ti ADS1928R DB and DE2 Board connection Acquisition of electrodesBuilding GUI using Matlab Test & Debug 3w 2w

23. Schedule – Semester B Cont. Project book completion Semester B -Final Presentation 2w 1w