1. Useless Memory Allocation in System on a Chip Test: Problems and Solutions Paul Theo Gonciari Bashir Al-Hashimi Electronic Systems Design Group University of Southampton, UK Nicola Nicolici Electrical and Computer Engineering McMaster University, Canada

2. Overview Memory problems in SOC test Useless memory allocation (UMA) – Problems : Multiple scan chain designs Core wrapper design – Solutions : mUMA heuristic ATE deployment procedure Experimental results Conclusions

3. Why Test Data Reduction ? Exponential increase in volume of test data (ITRS) 60% of ATE upgrade caused by memory (EETimes) Solutions –Built-in self-test (BIST) –Test data reduction Useful – test data compression Useless

4. Useless Memory Allocation Problems Multiple scan chains - padded values S3 S2 S1 1xx010 010xxx first bit last bit 01000 1

5. UMA – Core Wrapper Design Core A WSC2 WSC3 WSC1 WSC4 tb2 tb3 tb4 tb1 5FF 8FF 12FF 11FF 12FF 11FF 8FF 5FF Solution 1

6. UMA – Core Wrapper Design Core A WSC2 WSC3 WSC1 WSC4 tb2 tb3 tb4 tb1 5FF 8FF 12FF 11FF 12FF 11FF 8FF 5FF Solution 2

7. UMA – Core Wrapper Design TS 2 TS 1 first bitlast bit 12FF 11FF 8FF 5FF Solution 2 useless memoryfirst bit 12FF 11FF 8FF 5FF Solution 1 Wrapper dependent Complex control Wrapper independent Simple control

8. mUMA – minimum UMA heuristic 1.Partition the wrapper scan chains (WSC) 2.Design a core wrapper minimum area (mA) heuristic compute UMA 3.Select the design with minimum UMA

9. mA – minimum Area heuristic Order SC in descending order Assign SC to WSC such that –maximum WSC remains the same –minimize area for selected partition Otherwise, select minimum WSC Compute UMA

10. 12FF mA – minimum Area heuristic 11FF 8FF 5FF WSCsSCs 1 2 3 11FF 4 8FF 5FF

11. mA – minimum Area heuristic 11FF 8FF 5FF 12FF WSCsSCs 1 2 3 4 12FF 8FF 5FF 11FF

12. ATE Deployment Procedure Requires 3 parameters –Maximum length partition ( max wsc ) –Difference (diff) –Split point (sp) Simple procedure TS 2 TS 1 12FF 11FF 8FF 5FF 12FF 11FF 8FF 5FF diff max wsc sp 041216 clk

13. mUMA performance

14. mUMA circuit s38584

15. Minimum Memory Requirements Comparison

16. Maximum Memory Requirements Comparison

17. Average Memory Requirements Comparison

18. Conclusions Illustrated the problem of Useless Memory Proposed a new methodology –mUMA core wrapper design algorithm –ATE deployment procedure Post-TAM optimization for minimum UMA Future work –Exploit the core wrapper design properties

19. DFT ATE Very low cost testers [Bedsole D&T01] –Reconfigurable memory pool –Reduced features per-pin – Memory management unit Sequencing per pin testers [Sivaram ITC01] –Clock and data control per group of pins – Central control unit

20. UMA - Core Wrapper Design – Case 2 wsc i = 11 wsc o = 12 10 FF 9 FF useless memory 10 FF 9 FF wsc i = 12 wsc o = 12 9 FF 10 FF TS 1 TS 2 9 FF 10 FF Solution 1 Solution 2