1. P1801 25-Dec-15 IEEE P1801 Working Group (Unified Power Format – UPF) Status Stephen Bailey Chair, P1801 Working Group

2. P1801 25-Dec-15 Agenda l Quick Background l Key Technical Objectives of P1801 l IEEE P1801 Schedule l Q&A

3. P1801 25-Dec-15 UPF Background l Initiated by users at DAC 2006 l Accellera sponsorship Sep 2006 l Donations from several companies Atrenta, Magma, Mentor, Synopsys, TI l Accellera approves v1.0 of UPF Feb 2007 l IEEE WG approved May 2007 l UPF version 2.0

4. P1801 25-Dec-15 Key Objectives of P1801 (v2.0) l As with any 1.0 version, there are bugs and ambiguities l Discovered by vendors while implementing tool support l By users working through “paper prototypes” of how they would use UPF for their design needs l Enhancements to (better) address needs missed in v1.0

5. P1801 25-Dec-15 Highlights of P1801 l Better support for soft IP & incremental refinement of low power specification l “Command layering” for incremental specification l Allow multiple calls to same command with each call adding more, but not contradictory, information l Enhanced retention specification l Save and restore are functions defined in terms of one or more signals

6. P1801 25-Dec-15 Highlights of P1801 (2) l Enhanced power state information l Consistent with incremental refinement l Planned deferment of details (placeholders) l Can be specified prior to having a completed supply network specified for implementation l More information for verification and analysis as well as more complete information for optimizing implementation l Transitions as well as states l Defined access to state information from HDLs l Allows reference to states and triggering on state changes in TB & within assertions

7. P1801 25-Dec-15 Support for Bias l Bias supplies l N-well, P-well, Deep-N-Well and Deep-P-Well l With defaults for each l New semantic definition: “corrupt-on-change” l A power state can be attributed with this semantic specification l Represents a bias voltage threshold that has uncharacterized performance l Nets and registers retain current value l But are corrupted on any change while in this state l Emulates that switching will occur but with an unknown timing

8. P1801 25-Dec-15 Enhanced Semantic Specification l Improved semantic specification for set_related_power_pin (Name may change.) l Simulation semantics specified as well as implementation l When used on input, has semantic of a constraint for the source connected to the input l Merge power domains

9. P1801 25-Dec-15 P1801 Schedule l Weekly telecons (Tues mornings) l Except for weeks with F2F meetings l May begin 2 nd set of weekly telecons to focus on technical issues to wrap-up l Monthly Face to Face Meetings l 15-17 Jan: Magma hosted in SJ l 25-27 Feb: Infineon hosted in Munich l 18-20 Mar: Synopsys hosted in Mountain View l Draft standard for WG review: l Feb 2008 l Enter IEEE ballot: l End of Mar 2008 l Complete balloting May/June 2008

10. P1801 25-Dec-15 Contact Information l p1801@eda.org: Email reflector p1801@eda.org l www.accellera.org/apps/org/workgroup/ p1801 www.accellera.org/apps/org/workgroup/ p1801 l Chair: stephen_bailey@mentor.com +1 30 37 75 16 55stephen_bailey@mentor.com