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High Speed Digital System Lab Final Presentation 1 semester project Instructor: Mony Orbach Students: Pavel Shpilberg Ohad Fundoianu
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Acquaintance and Learning noise sources and physical attributes of High Speed Digital Channels. Implementation of SerDes transceiver up to 3Gbps on ALTERA Stratix2GX SI Development board. Watching, measuring and understanding Signal Integrity phenomena. Design a high speed 4 channels transmitter for academic research.
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QUARTUS Stratix 2GX and Signal Integrity Development Board Agilent 8000B Series Infiniium Oscilloscope
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HS Digital Channel Definition: Amplitude Dependent Noise: CT, ISI, Timing, PS Independent Noise: Skin effect, Ohmic and Dielectric loss, EMI Jitter : RJ-DJ Example: CRU disturbed by Jitter
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PLL - Phase Locked Loop: Used for filtering noise and achieving high rates 8/10b - DC-balanced coding which prevents errors insures right sampling of the signal.
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memory Transmitter Scope Receiver FPGAGX FPGA Digital validation Analog validation
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Phase compensation Byte serializer * 8B/10B Encoder * Serializer PLL
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Word Aligner Deserializer PLL+CRU Byte Deserializer * 8B/10B Decoder * Rate matcher * Phase compensation
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Single Transiver with effective data rate of up to 3.25 Gbps. memory TransmitterReceiver Single Transiver with effective data rate of up to 6.375 Gbps. memory TransmitterReceiver Single Transiver with CRU (clock recovery unit) turned off. memory TransmitterReceiver clk Four transmiters on single chip- each one in different freq, and different line type (long,stripline, microstripline). memory Transmitter Receiver Features: Transfer data from memory to memory with high rate Features: The highest frequency possible on this transiver Features: Both transmitter and receiver get clocks (different ones). Synchronization depends on data. Features: Each transceiver in different block- requires different clock connection to each of the trancievers.
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Serial data 2496Mbps signal - 40” Line Regular StripLine
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Serial data 2496Mbps signal 40” Line Regular StripLine
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1248Mbps signal – Regular StripLine Clock signal Serial data
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Pre-Tap First Post-Tap Second Post-Tap
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Four random data outputs at 3.125 Gbps rate All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset, or turn down) The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on An output clock indicates when data cycle is done Data cycle length can be easily changed to any number (2 n-3 · 10 for all n) All four channels must be the same type (strip line)
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Transmiter XAUI Parallel clk mem counter mem
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