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MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” March 1st, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng.

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Presentation on theme: "MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” March 1st, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng."— Presentation transcript:

1 MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” March 1st, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

2 MICAS Department of Electrical Engineering (ESAT) Outline 1.Test chip finished 2. Theoretical analysis 3. Chip Testing proposal

3 MICAS Department of Electrical Engineering (ESAT) Test layout for EMI regulator done Layout transferred end of january, to be integrated in complete test chip. Taped out is/was when? One last change …

4 MICAS Department of Electrical Engineering (ESAT) Last change of the layout add extra output pin Vcontrol 1.Using metal 5 (can be cut in case of trouble) 2.Making measurements more flexible 3.Shaping the TF according to the values of Caux and Raux

5 MICAS Department of Electrical Engineering (ESAT) Outline 1.Test chip finished 2. Theoretical analysis 3. Chip Testing proposal

6 MICAS Department of Electrical Engineering (ESAT) Simplified model 4 nodes, difficult to analyze p1 p3 p2 z1

7 MICAS Department of Electrical Engineering (ESAT) Simplified model p1 p3 p2 Vi Ii Iout Short to ground

8 MICAS Department of Electrical Engineering (ESAT) Stability analysis - Small signal analysis Approximation: p1 p2 p3 z1 dominant pole second pole High frequency pole High frequency, left half-plane zero >3 for > 72° phase margin Gain of the current source Stability ~ Caux/Ctank

9 MICAS Department of Electrical Engineering (ESAT) Stability analysis – Simulation vs. Calculation Spectre simulation Maple calculation Raux=1.852K, Caux=20p,Ctank=100p Stability vs. Iload φ> 72 ° Iload =192.7u A

10 MICAS Department of Electrical Engineering (ESAT) Current TF analysis H(s)=Idd(s)/Iin(s) dominant pole second pole third pole High frequency zero left half-plane zero

11 MICAS Department of Electrical Engineering (ESAT) Current TF- simulation vs. calculation Spectre simulation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p Infinite Attenuation ?? Not in reality!

12 MICAS Department of Electrical Engineering (ESAT) Model revisited p1 p3 p2 z1 Cdb1

13 MICAS Department of Electrical Engineering (ESAT) Current TF- simulation vs. calculation Spectre simulation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p TF vs. Caux

14 MICAS Department of Electrical Engineering (ESAT) Maximum Attenuation Maple calculation Iload =80u A, Raux=1.852K, Ctank=100p TF vs. Caux Cut off freq. ~ 1/Caux Large attenuation requires Large Ctank and/or small Cdb1 Cascode structure !

15 MICAS Department of Electrical Engineering (ESAT) Caux/Ctank and time domain ∆Vdd ∆Vdd Caux = 1..5 pF Equations to be calculated However: ∆Vdd ~ Caux/Ctank in damped case

16 MICAS Department of Electrical Engineering (ESAT) Conclusion Regulator design criteria for Caux,Ctank  Stability ~ Caux/Ctank  Current transfer function (i.e. di/dt attenuation) Cut off freq: Gm/Caux Max. attenuation: Cdb1/(Cdb1+Ctank)  Time domain ∆Vdd Caux/Ctank Conclusion  Caux/Ctank determines stability and ∆Vdd. More stable also means a larger ∆Vdd !  Design for small Cdb1 Similar story possible for Gm, Gm1

17 MICAS Department of Electrical Engineering (ESAT) Chip Testing proposal Test: 1.List of tests for di/dt 2.Test setup proposal To be designed => test board 3. Will we also do the emission tests ?

18 MICAS Department of Electrical Engineering (ESAT) List of tests for di/dt For the special EMC regulator: 1.Current pulse measurement, 2. The current TF as a function of Ctank, Caux 3. Measurement of di/dt reduction vs. Ctank, Caux and decoupling cap, 4. Influence of different loads provided by AMIS -- D-FF or MS-FF -- number of gates -- distributed clocks over time ……

19 MICAS Department of Electrical Engineering (ESAT) Test setup for di/dt measurement 1. For di/dt transient measurement 1. OPAMP, BW ? 2. Current probe ? 3. Transformer ? DUT is EMI regulator EMI regulator + V-regulator

20 MICAS Department of Electrical Engineering (ESAT) Test setup for Transfer function 2. For Transfer Function measurement

21 MICAS Department of Electrical Engineering (ESAT) Design of Test Board To be designed … 1. OPAMP, BW ? 2. Current probe ? 3. Transformer ?

22 MICAS Department of Electrical Engineering (ESAT) Measurement of Emission IEC 61967-4 International Standard Spectrum Analyzer 1 Ohm IC Chip under test Outer side Inner side IEC 61967-2 International Standard radiated mode conducted mode 1/150 ohm method can be foreseen on testboard Do we need to measure this? How ?

23 MICAS Department of Electrical Engineering (ESAT) Future work 1. Test board ?, Chip measurement, Finish the theoretical analysis, 2. Continue research on the Clock strategy: SSCG

24 MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention

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