1. S. FUKUDA LCPAC 0603251 RF-Systems for STF S. Fukuda Accelerator Laboratory Content Introduction Status of STF and Plan forFY2006 LLRF Summary

2. S. FUKUDA LCPAC 0603252 Accelerator Laboratory Cryogenics For5MW 5MW For10MW 10MW CM( 35 MV/m)

3. S. FUKUDA LCPAC 0603253 Plan to Phase-1 (for 2 years) For #1-Modulator: Reinforce the modulator with bouncer circuit using the PNC modulators and 1:6 pulse-transformer making use of JHP pulse-transformer. Old IGBT is reused. PLC Control system is newly equipped.  Almost done For #2 modulator: New modulator which is capable to drive 10 MW MBK klystron is designed and manufactured. This is based on the TESLA Design. New device IEGT is promising.  Waiting the tender Two 5-MW Klystrons will be prepared. –Thomson TH2104A (1.296GHz in KEK used in JHP) is tested at 1.3GHz.  Under testing –Procurement of Thales TH2104C is under going as the replaceable klystron.  Purchased –If competitive budget or equivalent is approved, a multi-beam klystron will be introduced.  Planning in FY2006 Two kinds of power distribution is tested to compare the performance and cost.  under progressing LLRF system is prepared for the beam acceleration test.  under progressing Accelerator Laboratory

4. S. FUKUDA LCPAC 0603254 Specification of STF-RF KlystronTwo 5-MW klystrons (one for RF gun), 1.3 GHz, 125kV, 1.5ms(RF pulse width),5 Hz Repetition Modulator-1Reinforcement of PNC modulator IGBT SW, Pulse width of 1.7ms(voltage) 1:6 Pulse Trans. With Bouncer, flat top 1% Modulator-2New modulator / IGBT SW, Pulse width of 1.7ms 1:15 Pulse Trans. With Bouncer, flat top 1% Power Distribution System (PDS) 5MW power is fed into 8 cavities. Linear PDS / 3dB tournament PDS LLRFDigital feedback system using 10 x 16bit ADCs. IF=10MHz, Lo=1310MHz, Sampling 40 MHz. Amplitude stability ±0.1 ％ Phase stability ±0.1deg. Accelerator Laboratory, KEK

5. S. FUKUDA LCPAC 0603255 Concept of test facility for quick and inexpensive start utilizing existing properties Making use of power supply and waveguide component moved from PNC (Power Reactor and Nuclear Fuel Corp). Power supply has 3 modes; (1)Short pulse (100ms), (2)long pulse (4ms) and (3)CW for the modulating anode type klystron. For mode(2), possible klystron is modulating anode type TH2115 (Thales). About 2MW output is possible for this case. Reform to (PT+Bouncer) allows to use TH2104A(C). Photo of Modulator in PNC Block diagram of PNC modulator ５－１０ MW Accelerator Laboratory

6. S. FUKUDA LCPAC 0603256 Modulator Development Install of Pulse transformer Waveform of modulator without bouncer Modulator reformation was almost done and started operation for coupler test. Reformation was performed as half the price as the newly built modulator. Bouncer circuit will be added in middle of April in 2006. Accelerator Laboratory

7. S. FUKUDA LCPAC 0603257 Candidate Klystrons (1.3GHz 、 Long Pulse) 10 MW Peak 5-10 MW Accelerator Laboratory

8. S. FUKUDA LCPAC 0603258 Klystron test status (1) Performance of the klystron, which was bought 15 years ago, was checked in short pulse operation(3micro sec pulse width) Waveform: voltage (top), Current (bottom) Applied voltage (kV) Accelerator Laboratory

9. S. FUKUDA LCPAC 0603259 Klystron Test-Photo of test station and long pulse test IGBT Sw Cabinet Pulse Transformer Tank Klystron High Power Circulator High power Water Load Variable Shorted WG Coupler Insertion Points RF waveform measured in 060301 RF Window Accelerator Laboratory

10. S. FUKUDA LCPAC 06032510 Modulator and klystron plan in FY2006  Modulator New modulator (#2) based on the ILC-BCD type will be manufactured. Preparation of the tender is under going. Full completion depends on budget.  Klystron  Second TH2104C (5MW tube) will be conditioned for the waveguide components’ evaluation or RF gun test.  Collaboration of the 10MW-MBK, especially of the horizontally mounted MBK, with Toshiba Corp. is considered. It is also depends on the budget.  Design work of the 10 MW-MBK with the 36 beam-lets which is operated in 50 kV are planed. Collaboration between KEK and Russian engineers is under going. Accelerator Laboratory

11. S. FUKUDA LCPAC 06032511 Coupler test configuration Usual test terminated by a high power load Durability test under the large reflection power. High-power circulator is required to protect the klystron Accelerator Laboratory Waveguide Layout and coupler test Coupler developed by Kako etc.

12. S. FUKUDA LCPAC 06032512 Phase-1 Cavity Test WG Configuration Accelerator Laboratory Another type of PDS, which is possible to change the phase and Qext of the cavities independently, should be also studied. At first, 8 circulators will be used to have an initial test.

13. S. FUKUDA LCPAC 06032513 J-PARC based LLRF system Digital FB system using a FPGA board LLRF PLC system control digital FB system 400 W Amp. Digital FB cPCI system will be installed in Aug.2006 LLRF system @STF Phase1 Arc sensor Fast Interlock Klystron linerlizer Power meter Accelerator Laboratory

14. S. FUKUDA LCPAC 06032514 Digital LLRF FB control @STF Phase1 J-PARCSTF Phase-1 CavityNormalSuper Frequency 324 MH ｚ 1300 MH ｚ Q-value2e42e6 Rise time100 us500 us Pulse width650 us1.5ms Phase difference ～ 30deg. ～ 60deg. Pulse voltageLorentz detuning othersMicrophonics Amp. Stability ±1 ％ ±0.1 ％ Phase stability±1deg.±0.1deg. FB loop ＜ 1us ＜ 3us JPARC linac LLRF 4x14bit ADCs 324 MHz Max. 2 cav. IF=12 MHz LO=312 MHz Sampling=48 MHz STF phase-1 10x16bit ADCs 1300 MHz Max. 8 cav. (rocketIO) IF=10 MHz LO=1310 MHz Sampling=40 MHz STF phase-2 1300 MHz Max. 36 cav. IF=10 MHz LO=1310 MHz Sampling=40 MHz Digital cavity simulator Achieved stability of ~+-0.1%, ~+-0.05deg. @J-PARC Amplitude:6000, phase:0deg. Accelerator Laboratory

15. S. FUKUDA LCPAC 06032515 FPGA & DSP boards @STF Phase1 10 16bit-ADCs FPGA 2DACs Quench etc. Output max RF off (by diagnostics in DSP) Real time intelligent diagnostics by DSP board Custom FPGA board : Mezzanine card of the commercial DSP board 10 16bit-ADCs and 2DACs + 2Rocket IO 40 MHz clock Commercial DSP board (Barcelona) (same to J-PARC system) :4x TI C6701 DSPs Can access to FPGA like an external memory of DSP Accelerator Laboratory

16. S. FUKUDA LCPAC 06032516 Cavity Simulator: by commercial FPGA board (Finished) FB program development （ ~2006.Dec ） FB operation （ 2006 Dec. ） Software development plan for STF- Phase1 FB algorism (software development) Real Cavities Accelerator Laboratory

17. S. FUKUDA LCPAC 06032517 Now, the number of ADCs in a FPGA board is limited due to the substrate. (maybe ~15 with 16 layers in substrate) The idea is based on the ‘digital radio’ and obtaining cavity signals with a ADC. Mixture of two signals decrease the resolution of analog signals but averaging increases the resolution. Proposal of IF mixture Over-sampling: IF 8 MHz & 12 MHz with 48 MHz sampling -> include averaging effect ->increase resolution Cavity signals do not change during averaging (due to high Q values) → Enough IF separation Accelerator Laboratory

18. S. FUKUDA LCPAC 06032518 LLRF schedule (analog llrf and MPS) Analog llrf (amplifier, etc.): finished MPS: almost finished (except modification for 8 cavities) PLC program improvement (MPS, for 8 cavities): ~ Aug.,2006 (digital FB system) FPGA/DSP/Host program development: ~June 2006 Brash-up of feedback algorithm by cavity simulator: July,2006-Aug.,2006 Installation of digital FB system to STF: Aug.,2006 Test operation at STF with cavity simulator: ~Dec. 2006 Host/Data acquisition software development: ~Dec. 2006 Accelerator Laboratory

19. S. FUKUDA LCPAC 06032519 Summary In FY2005, RF system for STF has been developed as planed in the beginning. Reformation of the PNC modulator has almost done and performed the klystron test. Bouncer circuit will be installed in middle of April. First coupler test will be scheduled in April. Klystron bought 15 years ago was evaluated and operated normally. Plan of the FY2006 for modulator and klystron are shown. New modulator is now under the preparation of tender. Development of MBK is also seriously considered. LLRF is under manufactured based on the technology developed in J-PARC. Analogue system of LLRF has installed and already operated. Digital LLRF system are developed. Digital FB hardware for STF Phase-1 was completed and installed. Cavity simulator and software development are scheduled in this spring to autumn. Accelerator Laboratory