1. 1 EPO3-A3: Dora Dora Delta One Recreation Attempt Arjen KremersBart Hettema Danny ElderingHann Mai Truong Joris BelierPiet De Vaere Tim HosmanTimothy de Moor

2. 2 EPO3-A3: Dora Specifications Delta I Microprocessor 8-bit databus 10 data registers 16 instructions 6.1 MHz Overview

3. 3 EPO3-A3: Dora Specifications User I/O 13-bit instructions EEPROM Compared to Delta I

4. 4 EPO3-A3: Dora Specifications Program counter ALU Data registers Flow Control Unit Decoder I/O register Memory Control Unit User Control Module Top-level Test tools Test plan Components

5. 5 EPO3-A3: Dora Program Counter Specification

6. 6 EPO3-A3: Dora 6 ALU & Accumulator Design

7. 7 EPO3-A3: Dora 7 ALU & Accumulator Results

8. 8 EPO3-A3: Dora DREG Temporarily stores data 10 data registers 8-bit tristate buffer Input from DEC ld : load data in a register oe : enable an output buffer Data Register

9. 9 EPO3-A3: Dora FCU Facilitates user confirmation 13th instruction bit of MCU data Bit ‘0’  execute instruction Bit ‘1’  waiting for user Opcode hold/passed to DEC Generate signals: pc_en and mcu_ack Flow Control Unit

10. 10 EPO3-A3: Dora DEC Input receives 12 bit instruction 0000 [4-bit Opcode] 10101010 [8-bit Operand] To process this instruction different modules are required. The decoder enables the different modules based upon the instruction given. No FSM needed Collection of logic gates. Decoder

11. 11 EPO3-A3: Dora The I/O-Registers I/O multiplexer circuit implementation Input and output of the chip

12. 12 EPO3-A3: Dora

13. 13 EPO3-A3: Dora The I/O-Registers Loading in registers Reading from registers Multiplexer The implementation on the chip

14. 14 EPO3-A3: Dora MCU EEPROM Controller MCU cycle: 8 clock cycles send read command 0000A 8 010 8 clock cycles send address A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 13 clock cycles receive data Raise data_rdy until data_ack is high Instruction stored in two bytes PC to 256  512 bytes  9-bit address Memory Control Unit

15. 15 EPO3-A3: Dora MCU Custom VHDL EEPROM simulation Custom made test board Arduino EEPROM writer Logic analyser Testing

16. 16 EPO3-A3: Dora UCM Falling edge detector Halts process until user releases button User Confirmation Module

17. 17 Challenge the future Modified version of the Delta I assembler Difference in output stage VHDL or C++ 13 th instruction bit Tools developed for testing Assembler

18. 18 Challenge the future Instructions from external EEPROM System required to write instructions 4K SPI Bus Serial EEPROM 25AA040A 512 bytes storage Arduino SPI protocol library New library added Tools developed for testing EEPROM SPI writer

19. 19 Challenge the future Test after writing the EEPROM Read and print all stored bytes Breadboard Unreliable  soldered board Block protect flag Tools developed for testing EEPROM SPI writer

20. 20 Challenge the future GCD application Works?  chip works Hypothesis of malfunction Specific custom assembly code External test signals Testplan

21. 21 EPO3-A3: Dora Top-level Layout

22. 22 Challenge the future mcu_rdy pc_new pc_en pc_ld pc_inc clk ss Logic level Switch level regproc: process begin wait until rising_edge(clk); if (res = '1') then pc_new <= '0'; else pc_new <= new_output; end if; end process; newproc: process (pc_ld, pc_inc, pc_en) begin if ((pc_ld or pc_inc) and pc_en) = '1' then new_output <= '1'; else new_output <= '0'; end if; end process; mcu_rdy pc_new pc_en pc_ld pc_inc clk ss

23. 23 Challenge the future FPGA Demo

24. 24 Challenge the future FPGA Demo ; Get input gcd: ld R10 st R0 ld R11 st R1 loop: ld R1 and 11111111b bz done ld $+3 st R3 jp mod ld R1 st R0 ld R2 st R1 jp loop done: ld R0 st R10 jp gcd ; Calculate mod mod: ld R0 st R2 subtr: ld R1 xor 11111111b set c add R2 st R2 and 10000000b bz subtr ld R2 clr c add R1 st R2 jp R3

25. 25 EPO3-A3: Dora Dora Delta One Recreation Attempt Arjen KremersBart Hettema Danny ElderingHann Mai Truong Joris BelierPiet De Vaere Tim HosmanTimothy de Moor