1. M.Mohajjel

2. Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design

3. Reprogrammable PLDs Updating a device or correction of errors Reuse device for a different design Ideal for course laboratories 3Digital System Design

4. Programmable Read-Only Memory (PROM) Single level of programmability Fixed AND-array Programmable OR-array Digital System Design4 0 1 2 3. 28 29 30 31 I0I1I2I3I4I0I1I2I3I4 A7 A6 A5 A4 A3 A2 A1 A0 5-to-32 decoder

5. Programmable Read-Only Memory (PROM) Example Digital System Design5 InputsOutputs I4I3I2I1I0A7A6A5A4A3A2A1A0 0000010110110 0000100011101 0001011000101 0001110110010...... 1110000001001 1110111100010 1111001001010 1111100110011 0 1 2 3. 28 29 30 31 I0I1I2I3I4I0I1I2I3I4 A7 A6 A5 A4 A3 A2 A1 A0 5-to-32 decoder x xxx x x x x x x xx x xx x x x xx x xx x x x x x x x

6. Field-Programmable Logic Array (PLA) Two levels of configurable logic Programmable AND-array Programmable OR-array Digital System Design6

7. Field-Programmable Logic Array (PLA) Example Digital System Design7

8. Programmable Array Logic (PAL) Single level of programmability Programmable AND-array Fixed OR-array Digital System Design8

9. Programmable Array Logic (PAL) Example Digital System Design9 W = A B C’ + A’ B’ C D’ X = ? Y = ? Z = ?

10. Simple PLDs (SPLDs) Digital System Design10 Fixed AND array (decoder) Programmable OR array Programmable connections Outputs Inputs Programmable read-only memory (PROM) Programmable AND array Fixed OR array Programmable connections Outputs Inputs Programmable array logic (PAL) device Programmable logic array (PLA) Programmable AND array Programmable OR array Programmable connections Outputs Inputs Programmable connections

11. Sequential Programmable Devices Digital System Design11

12. Complex PLDs (CPLDs) Two levels of programmability PLD like blocks Global interconnection matrix Digital System Design12

13. Field-Programmable Gate Arrays (FPGAs) An array of uncommitted circuit elements, called logic blocks, and interconnect resources Three elements Logic blocks I/O blocks Interconnections Wires Switches Digital System Design13

14. FPGA Logic Blocks LUT-Based (look-up table) Mux-Based (multiplexer) Digital System Design14

15. Digital System Design15

16. Digital System Design16

17. Digital System Design17

18. User-Programmable Switch Technologies Fuse Used in PLAs Floating gate transistors Used in CPLDs Digital System Design18

19. User-Programmable Switch Technologies (cont.) SRAM-controlled Programmable Switches Used in FPGAs Advantages Easily changeable Track latest SRAM technology Disadvantages Volatile High Power dissipation Digital System Design19

20. User-Programmable Switch Technologies (cont.) SRAM-controlled Programmable Switches Programmable connections Pass-transistor Transmission gate Multiplexer Digital System Design20

21. User-Programmable Switch Technologies (cont.) Anti-fuse Used in FPGAs Modified CMOS technology Originally open-circuits Digital System Design21

22. User-Programmable Switch Technologies (cont.) Anti-fuse Advantages Less expensive than SRAM technology Low delay Low power dissipation power Disadvantages One-Time Programmable (OTP) Digital System Design22

23. User-Programmable Switch Technologies (cont.) Anti-fuse Advantages Less expensive than SRAM technology Low delay Low power dissipation power Disadvantages One-Time Programmable (OTP) Digital System Design23

24. Evolution of Programmable Logic Devices User-Programmable Switch Technologies (cont.) Digital System Design24

25. Designing Logic with FPGAs Digital System Design25 Mapping Placement Routing

26. Designing Logic with FPGAs (cont.) Mapping Example : Using 3-LUTs Digital System Design26

27. Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Digital System Design27 Programming Bit File

28. Altera CPLDs MAX 7000 Logic Array Blocks (LABs) Programmable Interconnect Array (PIA). Digital System Design28

29. Altera CPLDs MAX 7000 LAB Two sets of eight macrocells Digital System Design29

30. Xilinx XC4000 FPGA Configurable Logic Block (CLB) Digital System Design30

31. Xilinx XC4000 FPGA (cont.) Interconnect structure Digital System Design31

32. Altera FLEX 8000 FPGA Logic Element (LE) Digital System Design32

33. Altera FLEX 8000 FPGA (cont.) Carry Chain Digital System Design33

34. Altera FLEX 8000 FPGA (cont.) Cascade Chain Digital System Design34

35. Altera FLEX 8000 FPGA (cont.) Logic Array Blocks Local interconnect Digital System Design35

36. Altera FLEX 8000 FPGA (cont.) FastTrack (global interconnect) Digital System Design36

37. Altera FLEX 10000 FPGA (cont.) Embedded Array Blocks Digital System Design37

38. Altera FLEX 10000 FPGA (cont.) EAB structure Digital System Design38

39. Xilinx Spartan-6 FPGA CLB Digital System Design39

40. Xilinx Spartan-6 FPGA SLICE Digital System Design40

41. Xilinx Spartan-6 FPGA SLICE Digital System Design41

42. Xilinx Spartan-6 FPGA SLICE Digital System Design42

43. Xilinx Spartan-6 FPGA LUT6 Digital System Design43

44. Xilinx Spartan-6 FPGA LUT6 Digital System Design44

45. Xilinx Spartan-6 FPGA Shift register lookup table (SRL) Digital System Design45

46. Xilinx Spartan-6 FPGA SLICEM Used as Distributed Memory Digital System Design46

47. Xilinx Spartan-6 FPGA Block RAM Digital System Design47

48. Xilinx Spartan-6 FPGA DSP48A1 Slice Digital System Design48

49. Xilinx Spartan-6 FPGA Interconnect Channels Digital System Design49

50. Computer Aided Design (CAD) Flow for FPDs Digital System Design50

51. System on a Chip Add Embedded Micro-Processor Cores in Fabric e.g. RISC PowerPC Ethernet Interface Run Operating System e.g. Linux Combine Micro-Processor & Massively Parallel Logic Dual Design Flows Firmware HDL Software C Digital System Design51