1. 1 Semiconductor Memories

2. 2 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

3. 3 Memory Timing: Definitions

4. 4 Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

5. 5 2D Memory Architecture A0A0 Row Decoder A1A1 A j-1 Sense Amplifiers bit line word line storage (RAM) cell Row Address Column Address AjAj A j+1 A k-1 Read/Write Circuits Column Decoder 2 k-j m2 j Input/Output (m bits) amplifies bit line swing selects appropriate word from memory row

6. 6 Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

7. 7 Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

8. 8 Read-Write Memories (RAMs)  Static – SRAM  data is stored as long as supply is applied  large cells (6 fets/cell) – so fewer bits/chip  fast – so used where speed is important (e.g., caches)  differential outputs (output BL and !BL)  use sense amps for performance  compatible with CMOS technology  Dynamic – DRAM  periodic refresh required  small cells (1 to 3 fets/cell) – so more bits/chip  slower – so used for main memories  single ended output (output BL only)  need sense amps for correct operation  not typically compatible with CMOS technology

9. 9 Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1 default output = 0 MOS ROM 2 default output = 1 BL is pulled down to GND when on activation of WL

10. 10 MOS OR ROM WL[0] V DD BL[0] WL[1] WL[2] WL[3] V bias BL[1] Pull-down loads BL[2]BL[3] V DD

11. 11 MOS NOR ROM WL[0] GND BL[0] WL[1 ] WL[2 ] WL[3 ] V DD BL[1] Pull-up devices BL[2]BL[3] GND

12. 12 MOS NOR ROM Layout Programming using the Active Layer Only, Active mask in fabrication process Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 ) WL[0] GND WL[1 ] WL[2] GND WL[3 ] using diffusion for GND

13. 13 MOS NOR ROM Layout Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (11 x 7 ) Programmming using the Contact Layer Only selective addition of metal-to-diffusion contacts WLWL [0] GND WLWL [1] WLWL [2 ] GND WLWL [3]

14. 14 MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

15. 15 Equivalent Transient Model for MOS NOR ROM  Word line parasitics  Wire capacitance and gate capacitance  Wire resistance (polysilicon)  Bit line parasitics  Resistance not dominant (metal)  Drain and Gate-Drain capacitance Model for NOR ROM V DD C bit r word c WL BL

16. 16 Equivalent Transient Model for MOS NAND ROM  Word line parasitics  Similar to NOR ROM  Bit line parasitics  Resistance of cascaded transistors dominates  Drain/Source and complete gate capacitance Model for NAND ROM V DD C L r word c c bit r WL BL

17. 17 Decreasing Word Line Delay driving from both sides reduces the worst case delay of the word line by 4 (like buffer insertion to reduce RC delay)

18. 18 Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Precharge devices BL[2]BL[3] GND pre f

19. 19 Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

20. 20 Floating-Gate Transistor Programming 0 V -5V 0 V DS Removing programming voltage leaves charge trapped 5 V -2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

21. 21 A “Programmable-Threshold” Transistor  Applying V WL results in either current to flow (“0” state) or not (“1” state)

22. 22 FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX (floating-gate tunneling oxide) transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

23. 23 EEPROM Cell WL BL V DD 2 transistor cell EEPROM cell as configured during read operation. When programmed, the threshold voltage of the FLOTOX is higher than V DD, disabling it. If not, it acts as a closed switch.

24. 24 Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

25. 25 Basic Operations in a NOR Flash Memory― Erase Electrons at the floating gate are ejected to the source by tunneling. Gate is at GND, Source is at 12 V

26. 26 Basic Operations in a NOR Flash Memory―Write For the write operation, a high voltage 12v is applied at gate and 6v applied at drain, i.e., BL to write a “1”. Hot electrons are injected into the floating gate, raising the threshold, effectively turning off the device. Floating gate has no electrons for “0” stste Floating gate has electrons for ‘1” state

27. 27 Basic Operations in a NOR Flash Memory― Read For a read operation, the selected word line is raised to 5V, turning on the transistor if “0” state stored, the transistor remains off if “1” state stored.

28. 28 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q Consumes power only when switching - no standby power (other than leakage) is consumed The major job of the pullups is to replenish loss due to leakage Sizing of the transistors is critical

29. 29 CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C First precharge both bit lines – BL and !BL – to 1 Then discharge !BL through M5 and M1 CR = (W/L) 1 / (W/L) 5 M5 with bigger L is desired

30. 30 SRAM Cell Analysis (Read) !BL=1 BL=1 WL=1 M1 M4 M5 M6 Q=1 !Q=0 C bit Read-disturb (read-upset): must carefully limit the allowed voltage rise on !Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints the resistance of M5 must be larger than M1 (M5 with bigger L, so that M1 is faster than M5)

31. 31 CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 Voltage rise [V] 11.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V) The voltage does not rise above the threshold for CR > 1.2 V dd = 2.5V V Tn = 0.5V

32. 32 CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL 1 is stored, trying to write a 0 In order to write the cell, the pass gate M6 must be more conductive than the M4 to allow node Q to be pulled to a value low enough for the inverter pair (M2/M1) to begin amplifying the new data. Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 )

33. 33 CMOS SRAM Analysis (Write) Pullup Ratio (PR) = (W M4 /L M4 )/(W M6 /L M6 ) V dd = 2.5V |V Tp | = 0.5V  p /  n = 0.5

34. 34 Cell Sizing  Keeping cell size minimized is critical for large caches  Minimum sized pull down fets (M1 and M3)  Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR  But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle  Minimum width and length pass transistors  Boost the width of the pull downs (M1 and M3)  Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger

35. 35 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

36. 36 Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD M 3 R L R L V WL QQ M 1 M 2 M 4 BL also known as the 4-transistor SRAM cell, reducing the SRAM size by one-third.

37. 37 SRAM Characteristics

38. 38 Multiple Read/Write Port Cell WL2 BL2 !BL2 M7M8 !BL1 BL1 WL1 M1 M2 M3 M4 M5M6Q!Q For the case of reads, with more than one pass gate open, the voltage rise in the cell will be larger and thus the size of the pulldown will have to be increased to maintain an acceptably low level (by a factor equal to the number of simultaneous open read ports).

39. 39 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V - V T  V V - V T BL2 1 X RWL WWL Core of first popular MOS memories (e.g., first 1Kbit memory from Intel). Cs is data storage (internal capacitance of wiring, M2 gate, and M1 diffusion capacitances Write: uses WWL and BL1

40. 40 Read: uses RWL and BL2. Assume BL2 precharged to Vdd (or Vdd- Vt). If cell is holding 1, then BL2 goes low – so reads are inverting. WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V - V T  V V - V T BL2 1 X RWL WWL Write: uses WWL and BL1 Refresh: read stored data, put its inverse on BL1 and assert WWL (need to do this every 1 to 4 msec)

41. 41 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

42. 42 1-Transistor DRAM Cell M1 X BL WL XV dd -V t WL write “1” BL V dd Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s CsCs read “1” V dd /2 sensing Read is destructive, so must refresh after read C BL

43. 43 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

44. 44 DRAM Cell Observations 1.1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. 2.DRAM memory cells are single ended in contrast to SRAM cells. 3.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. 4.Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. 5.When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

45. 45 Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated V PRE : precharged voltage 

46. 46 Static CAM Memory Cell If Bit=V DD and S = 0, then int charges up to through M3, Match discharge to “0” Match precharged to V DD

47. 47 CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers TagHit Address SRAM ARRAY Sense Amps / Input Drivers DataR/W

48. 48 Periphery Memory Circuit Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

49. 49 Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder _ _ _ _ _ _

50. 50 Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

51. 51 Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder All address signals are low during precharge precharge all outputs high, then GND inactive outputs - active “high” output signals

52. 52 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D 2-input NOR decoder

53. 53 Pass Transistor Based Column Decoder BL 3 BL 2 BL 1 BL 0 Data 2 input NOR decoder A1A1 A0A0 S3S3 S2S2 S1S1 S0S0  Advantage: speed since there is only one extra transistor in the signal path  Disadvantage: large transistor count !BL 3 !BL 2 !BL 1 !BL 0 !Data

54. 54 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

55. 55 Decoder for circular shift-register R signal resets the pointer to the first position

56. 56 Sense Amplifiers t p C  V  I av ----------------= make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

57. 57 Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

58. 58 Differential Sensing ― SRAM Precharge Bit lines to V dd by pulling pc low

59. 59 Latch-Based Sense Amplifier (DRAM) Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

60. 60 Charge-Redistribution Amplifier Concept M 2 M 3 M 1 V L V S V ref C small C large Transient Response

61. 61 Charge-Redistribution Amplifier― EPROM SE V DD WLC Load Cascode device Column decoder EPROM array BL WL V casc Out C out C col C BL M 1 M 2 M 3 M 4

62. 62 Single-to-Differential Conversion How to make a good V ref ?

63. 63 Open bitline architecture with dummy cells C S C S C S C S BLL LL 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE EQ Dummy cell

64. 64 DRAM Read Process with Dummy Cell 3 2 1 0 0123 V BL t (ns) reading 0 3 2 1 0 0123 V SE EQWL t (ns) control signals 3 2 1 0 0123 V BL t (ns) reading 1

65. 65 Voltage Regulator - + V DD V REF V bias M drive M V DL V V REF Equivalent Model

66. 66 Charge Pump

67. 67 DRAM Timing

68. 68 RDRAM Architecture memory array mux/demux network Data bus Clocks Column Row demux packet dec. Bus k k 3 l demux

69. 69 Address Transition Detection DELAY t d A 0 t d A 1 t d A N 2 1 V DD ATD …

70. 70 Reliability and Yield

71. 71 Sensing Parameters in DRAM From [Itoh01] 4K 10 100 1000 64K1M16M256M4G64G Memory Capacity (bits/chip) C D, Q S, C S, V DD, V smax C D(1F) C S Q S(1C) V smax(mv) V DD(V) Q S 5 C S V DD /2 V smax 5 Q S /(C S 1 C D )

72. 72 Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

73. 73 Open Bit-line Architecture —Cross Coupling Sense Amplifier C WL 1 BL C C WBL C CC WL 0 C C BL CC WL D D 0 1 BL EQ

74. 74 Folded-Bitline Architecture

75. 75 Transposed-Bitline Architecture

76. 76 Alpha-particles (or Neutrons) 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO 2 1 1 1 1 1 1 2 2 2 2 2 2

77. 77 Yield Yield curves at different stages of process maturity (from [Veendrick92])

78. 78 Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

79. 79 Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 0 = 3

80. 80 Redundancy and Error Correction

81. 81 Sources of Power Dissipation in Memories PERIPHERY ROW DEC selected non-selected CHIP COLUMN DEC nC DE V INT f mC DE V INT f C PT V INT f I DCP ARRAY m n m(n 2 1)i hld mi act V DD V SS I DD 5S C i D V i f 1S I DCP From [Itoh00]

82. 82 Data Retention in SRAM (A) SRAM leakage increases with technology scaling

83. 83 Suppressing Leakage in SRAM SRAM cell SRAM cell SRAM cell V DD,int V DD V V DDL V SS,int sleep SRAM cell SRAM cell SRAM cell V DD,int sleep low-threshold transistor Reducing the supply voltage Inserting Extra Resistance

84. 84 Data Retention in DRAM From [Itoh00]

85. 85 Case Studies  Programmable Logic Array  SRAM  Flash Memory

86. 86 PLA versus ROM  Programmable Logic Array structured approach to random logic “two level logic implementation” NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM!  Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA’s has drastically reduced 1.slow 2.better software techniques (mutli-level logic synthesis) But …

87. 87 Programmable Logic Array GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND-planeOR-plane Pseudo-NMOS PLA

88. 88 Dynamic PLA GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND f f OR f f AND-planeOR-plane

89. 89 Clock Signal Generation for self-timed dynamic PLA f t pre t eval f AND f f f f OR f (a) Clock signals(b) Timing generation circuitry Dummy AND row

90. 90 PLA Layout

91. 91 4 Mbit SRAM Hierarchical Word-line Architecture

92. 92 Bit-line Circuitry Bit-line load Block select ATD BEQ LocalWL Memory cell I/O line I/O B/T CD Sense amplifier CD I/O B/T

93. 93 Sense Amplifier (and Waveforms) BS I/OI/O DATA Block selectATD BSSA BS SEQ De i I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

94. 94 1 Gbit Flash Memory From [Nakamura02]

95. 95 Writing Flash Memory Read level (4.5 V) Number of cells 10 0 0V1V2V Vt of memory cells 3V4V 10 2 4 6 8 Evolution of thresholds Final Distribution From [Nakamura02]

96. 96 125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump 16896 bit lines 32 word lines x 1024 blocks From [Nakamura02]

97. 97 125mm 2 1Gbit NAND Flash Memory  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block From [Nakamura02]

98. 98 Semiconductor Memory Trends (up to the 90’s) Memory Size as a function of time: x 4 every three years

99. 99 Semiconductor Memory Trends (updated) From [Itoh01]

100. 100 Trends in Memory Cell Area From [Itoh01]

101. 101 Semiconductor Memory Trends Technology feature size for different SRAM generations