1. R. Fantechi

3. Cream specifications

4. Prototype board

5. ANALOG TESTS On of the first issues to be addressed is to check the quality of the analog signal and its digitisation by verifying that the CREAM complies with the parameters specified in the tender MARCH 27th:CREAM DELIVERED AT CERN MOST IMPORTANT PARAMETERS: Effective number of bits(ENOB) >10 Integral non-linearity < 5 LSB Differential non-linearity < 2 LSB Cross-talk < 70 dB Noise level/channel < 2 LSB Common mode noise < 2 LSB Rise time 40 ns, 70 ns FWHM Gain uniformity within 1%

6. ENOB measurement What is ENOB? Given a N bit ADC, the ENOB variable represents the number n(<N) of bits which are effective for the sampling, once the bits interested by the noise in the sampling process are subtracted Input signal: 5 MHz sine wave. Filter before CREAM input to quench higher-order frequencies Ad-hoc CREAM firmware used: upon request from the PC (ethernet packet) 65K samples are collected Sine wave generator is phase- locked with the CREAM clock to allow for an integer number of sine periods within the collected sample (required by FFT) DIGITAL FILTER FILTER+CREAM FILTER BANDWIDTH SINE & CLOCK GENERATORS

7. ENOB measurement How to compute ENOB: Feed a 5 MHz wave in the digital filters. The dynamic range should be as wide as possible (safety factor of 10 ADC counts from the edges used here) Collect the samples and feed a histogram, each bin corresponding to the sampling index Perform a Fast Fourier Transform (FFT) to compute the relevance of each harmonic in the histogram. As the sampling is @ 40 MHz, the highest measurable harmonic is 20 MHz (Nyquist theorem) Compute the SINAD (Signal to Noise And Distortion ratio), i.e. the ratio of the 5 MHz harmonic and the sum of other harmonics Compute the ENOB as: NOISE: the output of channels not pulsed is looked at. The noise (xtalk) should not exceed 70 dB according to specifications DIGITISATION FFT

8. CHANNEL 0 PULSED nearby channels (1,2,3) show a noise above the specifications small peaks at low frequencies in some channels to be understood (maybe from a DC-DC converter?) Components @ 10,15 MHz in the pulsed channel ENOB within specification ENOB DISTRIBUTION (150 EVENTS) CHANNEL 0-15 (upper connector)

9. CHANNEL 9 PULSED The crosstalk “follows” the pulsed channels CHANNEL 0-15 (upper connector)

10. DNL INL THEORETICAL VS EXPERIMENTAL DISTRIBUTION NON-LINEARITIES CHANNEL 12 INL, DNL well within the specifications, is similar to what reported in the ADC manual INL and DNL from ADC manual Differential and integral non-linearities measured using a statistical method, feeding a sinewave with an amplitude slightly larger than the dynamic range, in order to populate all bit codes. From the histograms of codes, with a set of formulae, one can extract DNL and INL

11. NON-LINEARITIES CHANNEL 8 Some channels seem worse than others, but still within specifications. Maybe it might be worth collecting more data to see finer structures

12. CROSSTALK The value of the crosstalk in the channels close to the pulsed one exceeds the specifications (<70 dB). What is responsible for this? A. Romboli: “the main source of cross-talk is the DB50 connector” TEST: pulse the lower channel (15) on the upper connector, see how the upper channels of the lower connector behave. The pattern of the first two of these channels (16,17) is very close to that of the pulsed channel, so if the crosstalk is due to the PCB it should show up anyway. DAUGHTERBOARD: FRONT SIDE (ODD CHANNELS) DAUGHTERBOARD: REAR SIDE (EVEN CHANNELS)

13. Crosstalk RESULT: adiacent channels show very limited or non-existent crosstalk. The large crosstalk detected is very likely to be due to the connector. SOLUTION : Andrea will use a different connector for the pre-production (10 boards). With this modification, the crosstalk should decrease sensibly CHANNELS 8-15 CHANNEL 15 PULSED CHANNELS 16-23 Probably due to PCB-transmittted noise, but compliant with specifications

14. SINGLE/COMMON MODE NOISE According to the tender, the noise level per channel and the common mode noise should be measured. Use both pedestal and a transceiver output-like signal, from the function generator Delay of the trigger to the CREAM was set with a timing unit: not good, at least 0.1% error on the delay. With 5 ms delay this is O(usec), then the signal was moving in the readout window Fixed with an update of the TALK firmware to digitally delay the signal These measurements allow also the check of the shaped pulse width

15. Pedestals Pedestal distributions channel 0-15 Incoherent and coherent noise

16. Pulsed channels Pedestal distributions channel 0-15

17. Pulse shapes Shapes channel 0-15 Channel 0 pulsed Shape channel 0

18. FIRMWARE UPDATES Several updates received from CAEN and tested since the last meeting 09/04/2013: Continuous firmware (65K consecutive samples sent upon request) 23/04/2013: Retrieval of destination IP/MAC from request packet 20/05/2013: First implementation of trigger sum links (TO BE TESTED) 17/06/2013: Working implementation of ARP and IP multicast communication + first basic zero suppression mechanism (to be tested during the dry run) Ongoing test activities on CREAM firmware/software: daily collaboration with CAEN people to solve problems and patch bugs NEXT FORESEEN FW UPDATES: Choke-error functionalities VME download of the CREAM firmware Improved zero suppression

20. Introduction: Requirements  FUNCTIONALITY - 32 trigger tiles per TE62 / 16 trigger tiles per TEL62 mezzanine 2 mezzanine cards per TEL62 which will be named: “TELDES” 16 bit @ 40 MHz per tile 8 ethernet cables (Cat5e or cat6) per CREAM to be received 16 Deserializer DS92LV16 (To TEL62 FPGA) 16 Equalizer DS15EA101 (Data from CREAM to Deserializer) 16 CLK to the TEL62 FPGA  PROTOTYPE PHASE 4 CARDS: 2 TO ASSEMBLE 1 TEL62 + 2 Cards SPARE  FIRST RELIABILITY TESTS  Digital performance: bit error rate (BER) using LVDS-18B-EVK (complete kit for evaluation of National SerDes devices DS92LV18) Mauro.piccini@pg.infn.itJune 2013

21. Prototype developments Mauro.piccini@pg.infn.itJune 2013 Mezzanine Board “TELDES” 8 ethernet cables per board RJ45 terminated

22. Prototype developments Mauro.piccini@pg.infn.itJune 2013

24. CPD racks, crates and modules All modules/crates dismounted, end May 31st Cable ends protected with bubble plastics SLM units dismounted, together with the adapter boards on the back of CPDs All the Fastbus and clock cables around have been removed Very few cables of the old installation will be left All the crates are now on ECN3 floor waiting a better packing and the move to the storage area Ready to start the new installation

27. Rack infrastructure Cooling: go to new heat exchangers Start with a reliable system New ones will be shorter: more space in the back to play with switches and cables Power distribution: new plugs to be mounted inside the racks to allow them to be closed Optical fibers: all installed First lot of VME crates delivered All powered and connected to the netowrk for DCS exercising

28. Channel checks We started some time ago a campaign of channel checks with calibration and scope, to spot possible problems with transceivers, power supply and (hopefully not) preamplifiers. Almost 10000 channels done Results to be analyzed The rest will be done soon After the replacement of a broken regulator board After the installation of the fibers

29. CREAM test bench @ 918 We have prepared a setup in the PC farm room mainly to test the CREAM networking firmware in conjunction with the PC farm A crate with up to now 1 prototype CREAM A switch of the final type, configured as it will be A fiber connection to the router A couple of general purpose PCs connected to it The CAEN PCI/VME interface and its software have been temporarily installed in the PC Farm user interface PC. It will be moved to a dedicated one soon This setup will be moved in ECN3 for the dry run to exercise the complete chain from the calibration pulses to the PC farm.

30. CREAM @ July 2013 dry run This setup will be moved in ECN3 for the dry run to exercise the complete chain from the calibration pulses to the PC farm. Connection to the TTC trigger and clock distribution Connection to the experiment network Acquisition of calibration pulses Delivery of data to the PC farm on request Specific implementation of IP multicast done It will be thoroughly tested Exercise the readout chain up to the maximum possible rate 100 KHz of L1 requests