1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Selected Topics in VLSI Design Results of Phase 1: First working FIR filter Design by Christoph Niemann and Vincent Wiese 30.10.2013 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Content Adder Multiplier Architecture Implementation Metric Future Improvements

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Adder Ripple-Carry-Adder Reference: Timmermann (2008): Script „Algorithmen der Datentechnik“ small easy to implement T = O(n) A = O(n) 40 bit data width for both summands and the sum

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Multiplier - Architecture Shift-and-Add Multiplier Inspired by:: Timmermann (2008): Script „Algorithmen der Datentechnik“ use of RCAs as CPAs T = O(coeff_width*data_width) A = O(coeff_width*data_width)

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Multiplier - Implementation Shift-and-Add Multiplier uses 40-Bit unshifted RCAs shift operation realized by filling in the data into the right position of the 40-Bit summands Extension for two‘s complement LSB‘s filled up with 0‘s MSB‘s filled up with either 1‘s or 0‘s depending on the MSB of the data word last summand is subtracted

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Metric Maximum Frequency:53,378 MHz Number of Slice Registers:762 Number of Slice LUTs:5321 Metric: 3,756*10 16 [Hz³]

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Future Improvements Direct Form II for the filter replace the unshifted 40-bit adder in the multiplier by shorter shifted ones  evade unnecessarry long critical path and waste of chip area use of redundant adders use of CSD-Recoding and Wallace-Trees in the multipliers

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Thank you for your attention!