Presentation is loading. Please wait.

Presentation is loading. Please wait.

Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece Logic cells and interconnect strategies for nanoscale.

Published byRoderick Holland Modified over 9 years ago

Similar presentations

Presentation on theme: "Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece Logic cells and interconnect strategies for nanoscale."— Presentation transcript:

1 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics I. O'Connor, K. Jabeur, D. Navarro, N. Yakymets Lyon Institute of Nanotechnology, Lyon, France P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy CEA-LETI-MINATEC, Grenoble, France nano.grain

2 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Outline Some technology fabric considerations Logic cells –Reduced-complexity dynamic standard cells –Reconfigurable logic cells and design methods Interconnect strategies –Matrix topologies –Island-style architecture –Metrics and comparisons Conclusions

3 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Explaining the jargon nanoscale computing fabric (nanoFabric): –nanoFabric: an array of connected nanoscale logic blocks (nanoBlocks) –nanoBlock: a circuit block containing programmable devices to compute boolean logic functions and means to route data usually hybrid approach (silicon die, or CMOS compatible): –bottom-up structure: chemical self-assembly for dense and regular arrangement of elements –top-down structure: conventional process options for interconnect or for computation –and memory …

4 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Double-gate ambipolarity In DG-CNTFETS, the I d -V g characteristic demonstrates ambipolarity –V bg > 0V: device behavior = n-type FET –V bg < 0V: device behavior = p-type FET –V bg floating / 0V: device is in the off state Verilog-A model developed (IMS) Reduced-complexity logic cells Ultra fine-grain reconfigurable logic cells Y.-M. Lin et al., IEEE Trans. Nanotechnology, 4(5),2005 -V +V -V on (n) off (n) on (p) off (p) GPGstate +V X0off (n/p)

5 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Hybrid technology "Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes", L. Ding et al., Nano Lett., 9(2), 800 (2009) "Monolithic integration of CMOS VLSI and carbon nanotubes for hybrid nanotechnology applications", D. Akinwande et al., IEEE Trans. Nanotechnology, 7(5), 636 (2008)

6 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Outline Some technology fabric considerations Logic cells –Reduced-complexity dynamic standard cells –Reconfigurable logic cells and design methods Interconnect strategies –Matrix topologies –Island-style architecture –Metrics and comparisons Conclusions

7 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Dynamic logic standard cells use the extra gate (PG) to reduce complexity function path includes EV phase transistor count: –2n (static logic) –n+2 (conventional DL) –n+1 (this work) clocking strategy: –Double clock (DCK) –Multiple clock (MCK) –Single clock (SCK) EV function path PC Out +V In 1 In 2 In n +V A B V bA V bB Y Pc gnd V dd Ev Layout flipping: rich set of operators

8 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr SCKMCKDCK Clocking strategies and cell variants PUN EV{0,+V}, PC{0,+V} Precharge: (PC=+V, EV=0) Evaluation: (PC=0, EV=+V) PUN EV+{0,+V}, EV-{0, -V}, PC{0,+V} mixed N- and P- function path: more complex functions function path PC EV- Out +V In 1 In 2 In n EV+ function path Clk Out +V In 1 In 2 In n -V function path PC EV Out +V In 1 In 2 In n PDN Clk{0,+V} Precharge: (Clk=0) Evaluation: (Clk=+V) complementary functions

9 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Comparison (simulation) V dd =1V f clk =3GHz, t r =t f =20ps, C L =150aF av. power +(0-20)% wc. delay -(30-50)% –no EV transistor, lower branch resistance pdp –(25-40)%

10 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Reconfigurable logic cell CNT-DR7T boolean data inputs A and B, data output Y {0,+V) four-phase non-overlapping clock signals PC 1, PC 2, EV 1, EV 2 {0,+V) ternary configuration inputs V bgA, V bgB, V bgC {-V,0,+V) EV 2 PC 2 EV 1 PC 1 t C Y f(A,B,V bA,V bB ) f(C,V bC )  = 1.5nm I off = 10 -13 A I on /I off =10 5 V bA A V bB B EV 1 PC 1 EV 2 PC 2 V bC V dd Y C J. Liu, I. O'Connor, D. Navarro, F. Gaffiot, El. Lett., 43(9), April 2007 V bgA V bgB V bgC Y +V -V +V -V +V -V +V -V +V -V +V -V +V -V +V -V A+B A.B A+B A.B A+B A A B B 1 0 +V0 0-V 0+V 0 -V 000 00

11 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Towards complete operator sets 1.5X-2X decrease in power consumption more functions, fewer transistors, one extra configuration signal DRLC-6T 15 functions DRLC-9T 16 functions

12 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Outline Some technology fabric considerations Logic cells –Reduced-complexity dynamic standard cells –Reconfigurable logic cells and design methods Interconnect strategies –Matrix topologies –Island-style architecture –Metrics and comparisons Conclusions

13 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Physical view: clusters of matrices

14 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Directed matrix interconnect topologies Mod_Omega_4d4w Baseline_4d4w Flip_4d4w Banyan_4d4w Adata inputs f rc B YY logic function data output (x2) configuration inputs

15 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Mapping success rate for matrices omega topology can achieve up to 25% more functions % exploitable cases 0-fault baseline 0-fault omega 0-fault flip 0-fault banyan 40%@12pt 20%-30%@12pt 90%@6pt 75%-80%@6pt

16 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Towards undirected topologies f 11 f 12 f 21 f 22 f 11 f 12 f 21 f 22 f 11 f 12 f 21 f 22 MetricsBanyanSystolic array Cross-cap Max. I/O data width / side---+ Intra-matrix connectivity--+ Total wire length wa+2a(w-1) Max. primary I/O path length wa+2a(w-1) Av. mapping success rate (2x2)61%58%66% Cross-capBanyanSystolic array

17 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr When to move to island-style? MetricsIsland-styleCell matrix No. transistors involved in mapping, T258375 % mapped matrices in a cluster75100 No. of switches added to connect matrices1680 Island-styleCell-matrix 1-bit FA application

18 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Wrap-up Logic with ambipolar DG-CNTFETS: –reduced-complexity dynamic-logic standard cells with –(25-40)% PDP –complete operator set dynamic-logic reconfigurable cells with low transistor count and power consumption Interconnect strategies: –directed matrix interconnect topology exploration –cross-cap topology proposed to relieve latency and data-directivity issues –matrices within islands allow efficient packing –routing between islands to be explored …

19 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Ambipolar double-gate FET BDD (A-BDD) for reconfigurable logic cells a 01 A BB F b c i k L d e f g h j Different edge value (reconfigurable) Shared edge value (non- reconfigurable) 5. Pass-transistor logic circuit implementation 4. Define implementation rules to implement the A-BDD into the circuit level 3. Label every edge connecting two different nodes 2. Combine their BDDs in a common A-BDD 1. Define output functions A-BDD of 2-inputs reconfigurable cell PTL reconfigurable cell (RSL-12T)  6X decrease in power consumption  Slightly improved time delay  Full functionality  More transistors  High number of config signals

20 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Methodology for mapping applications onto matrix-based nanocomputer architectures Aims: mapping applications onto selected architecture; obtaining diverse solutions with required area, power and delay; comparing different architectures Architecture Logic Cell, Matrix, Cluster Application n ≤ pi, m ≤ po Mapping application onto a matrix using GA Pi, number of primary inputs Po, number of primary outputs n, number of inputs m, number of outputs Partitioning Shannon’s expansion yesno Configuration for mapping matrices onto clusters Application Cluster architecture Application is mapped? yes Truth table Interconnection type Matrix size Cell characteristics no Mapping matrices onto clusters (e.g. VPR tool) 1. Mapping matrices using GA 2.1. Partitioning outputs 2.2. Partitioning inputs /Shannon exp.

21 Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece http://inl.cnrs.fr Methodology evaluation Normalized area, delay and track count Flow_1: ABC → T-VPack → VPR Flow_2: new methodology → VPR Two versions of a 1-bit full adder Version 1: 12 cells Version 2: 10 cells

Download ppt "Institut des Nanotechnologies de Lyon UMR CNRS 5270 ICECS 2010 – Athens, Greece Logic cells and interconnect strategies for nanoscale."

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.

NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.
2015-4-13 Based on text by S. Mourad Priciples of Electronic Systems Digital Testing: Design Representation and Fault Detection

Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection
Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: basic construction.
ECE 667 - Synthesis & Verification - Lecture 0 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits VLSI.

ECE Synthesis & Verification - Lecture 0 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits VLSI.
Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.
Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:

Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:
ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.
Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.
Optimal Layout of CMOS Functional Arrays ECE665- Computer Algorithms Optimal Layout of CMOS Functional Arrays T akao Uehara William M. VanCleemput Presented.

Optimal Layout of CMOS Functional Arrays ECE665- Computer Algorithms Optimal Layout of CMOS Functional Arrays T akao Uehara William M. VanCleemput Presented.
Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater.

Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater.
Programmable logic and FPGA

Programmable logic and FPGA
Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective
 2000 M. CiesielskiPTL Synthesis1 Synthesis for Pass Transistor Logic Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts,

 2000 M. CiesielskiPTL Synthesis1 Synthesis for Pass Transistor Logic Maciej Ciesielski Dept. of Electrical & Computer Engineering University of Massachusetts,
Chapter #6: Sequential Logic Design 6.2 Timing Methodologies

Chapter #6: Sequential Logic Design 6.2 Timing Methodologies
An Extra-Regular, Compact, Low-Power Multiplier Design Using Triple-Expansion Schemes and Borrow Parallel Counter Circuits Rong Lin Ronald B. Alonzo SUNY.

An Extra-Regular, Compact, Low-Power Multiplier Design Using Triple-Expansion Schemes and Borrow Parallel Counter Circuits Rong Lin Ronald B. Alonzo SUNY.
Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.

THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis.
CS 151 Digital Systems Design Lecture 38 Programmable Logic.

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

Similar presentations

Ads by Google