1. OPERA TT MEETING BRUSSELS, April 11, 2003 Status of the OPERA DAQ Status of the OPERA DAQ D.Autiero, J.Marteau T.Descombes  informatics S.Gardien, C.Girerd, C.Guérin  electronics

2. OPERA TT MEETING BRUSSELS, April 11, 2003 Ethernet mezzanine: Common part to all sub-detectors (TT, RPC, PT): the mezzanine is simply plugged on the digital boards (regardless of the standard used: VME for RPC & PT, dedicated board for the TT). Implementation: FPGA (readout sequencer), FIFO (temporary storage),  -processor (with Ethernet transceiver): MCM ETRAX from AXIS with imbedded LINUX. Dimensions: 60mm  60mm, 120 pins for external connections. Design completed  1 st version for mid-April. A dedicated test card is being produced in Lyon (electrical tests, tests of communication protocols). The up-to-date design has been circulated to the Naples group (RPC). Ethernet mezzanine

3. OPERA TT MEETING BRUSSELS, April 11, 2003 Ethernet mezzanine

4. OPERA TT MEETING BRUSSELS, April 11, 2003 TT digital board: This board is directly plugged at the output of the analog board (2 flat cables on connectors J7 & J8) Its main components are: 1 ADC (12 bits), 1 Ethernet mezzanine (FPGA, FIFO,  -processor), 1 clock receiver unit (EPLD), 1 high voltage module (ISEG) 1 LED pulser (from BERN) Dimensions: 282mm  90mm Connectors: 4 Ethernet RJ45 (2 for the clock, 2 for the signal), 1 (  7V), 1 RS232 (for debug purposes) Design under completion: 1st prototype for May. TT digital board

5. OPERA TT MEETING BRUSSELS, April 11, 2003 HV moduleLED pulser Ethernet mezzanine Analog board Clock EPLDRJ45 conn. We did not implement the Ethernet repeater in this 1 st prototype (cost, # I/O) !!!  we have 3 cables / digital board (clk, data, power supply) TT digital board

6. OPERA TT MEETING BRUSSELS, April 11, 2003 TT digital board Meeting @ CERN between Lyon & Bern : Review of all the parts of the digital board : LAL chips signals, ethernet mezzanine, LED pulser, HV module, clk receiver (fine tuning before freezing the board layout) Choice of all the components: ADC’s for charge R/O & for HV R/O, MUX, DAC’s, hold delay components Definition of the register R/O convention Review of all the signals & connectors from analog  digital board Discussion about the power supply : fuses ? monitoring ? cooling of the boards (temperature measurement with the 2nd ADC) ? Milestones: test with analog board  end of june (Bern also developping charge injector)

7. OPERA TT MEETING BRUSSELS, April 11, 2003 Backup DAQ system for : TT modules tests at IReS & prototype tests : Upgrade of a DAQ board designed for R&D purposes Uses an Ethernet transceiver from Agilent (BFOOT) 1 st prototype successfully tested (hardware & software based on Labview) 5 boards ordered (TT modules tests + tests in Gran Sasso)  should be received end of April FPGA ADC Ethernet transceiver (BFOOT) RJ45 Conn. NIM outputs TT digital board

8. OPERA TT MEETING BRUSSELS, April 11, 2003 Power supply distribution for TT (1 st proposal) : 2 solutions proposed by ALIMTRONIC based on Wiener products (PL500 modules used in D0 & Minos). Requirements:  7Vguaranteed for the last connected point, estimated power 10W / node  1.5A / node Most economical solution: 1 output for 2 walls (1 sense point between the 2 walls) 32 x 1.5 = 48A / output PL500 F8 / 48A : 6U power supply unit with 8 outputs  7.6 keuros / module 1 7U crate  1.4 keuros Pro : cost. Contra : important voltage fall along the line Other scheme : 1 output for 8 nodes (1/2 plane) 8 x 1.5 = 12A / output PL500 F8 / 12A : 3U power supply unit with 8 outputs  4.6 keuros / module 1 4U crate  0.9 keuros Pros & contra are inverted PL500: 48A To 2 nd wall  U2  U1 Umin=7V Sense point: Umax=Umin+  U1+  U2 Power supply distribution

9. OPERA TT MEETING BRUSSELS, April 11, 2003 General features : A common clock is distributed from the GPS master cards in the cavern to each node of OPERA The signal distribution is provided through M-LVDS bus (from the O/E converter to the master cards & from the master card to the node cards) The system is bi-directional (acknowledge signals + propagation time measurements to adjust delays) Commands are encoded in the clock (RESET, REBOOT, CYCLE INCREMENT) Clock distribution system

10. OPERA TT MEETING BRUSSELS, April 11, 2003 « Slave » clock in Hall C (receives the GPS signal from the Outside antenna though a 8km optical fiber) O/E converter card Master card 0 Node card i SM2 SM1 PCI card Optical fiber MLVDS Clock distribution system for TT (62 master cards, 992 nodes) 31 Master cards + 1 O/E converter card collected in 1 crate on the top of the detector (+3 additional master cards for the spectrometer) 1 optical fiber from the « slave » card / SM Clock distribution system

11. OPERA TT MEETING BRUSSELS, April 11, 2003 Master & node cards : Prototypes have been developped and successfully tested : Communication protocols (tested with more than 20 meters cables between master & node) Choice of serializer/deserializer components (Hotlink) VHDL code (for the ALTERA EPLD) The architecture of the node part has been frozen & implemented in the 1 st version of the TT boards Next step: production of 8 independant node cards (1/2 TT plane) to repeat tests with increasing load Prototype of master card Prototype of node card Clock distribution system

12. OPERA TT MEETING BRUSSELS, April 11, 2003 Cabling & co: The 1 st prototypes of TT board will not include local Ethernet repeaters. We foresee 2 repeaters / plane (1 left + 1 right) with 8 inputs & 1 output. We propose to collect the 62 outputs on 2 switches (with Gigabit output) on the top of the experiment to reduce the number of horizontal cables in the cable tray (only 2 Ethernet connections to the electronic room). In the 1 st scheme, the power supply modules will be located in 8 crates on one side of the experiment (the “most accessible” side) which will facilitate the cabling of the planes. The clock master cards + O/E converter will be hosted in 1 crate (standard to be defined) on one side of the experiment if this is compatible with the cable length (to be tested). Cabling & co.

13. OPERA TT MEETING BRUSSELS, April 11, 2003 12 boards RPC controller crate PT controller crate 11 boards 11 boards #0#30 16 nodes Optical fiber from slave card O/E converter Master cards Power supply crates #0#15 S.M. top view Ethernet switch Cabling & co.

14. OPERA TT MEETING BRUSSELS, April 11, 2003 GPS PCI card architecture (« slave » card in Hall C): Receives the GPS clock (we use a standard DATUM 637PCI antenna for tests). Distributes the clock through optical fibres & receives signals from the different nodes (2 lines / SM, no optical splitter). The idea is to design a new slave card using PCI standard with a “collaboration” from the ESAT company who designs the LNGS GPS system. A visit to the ESAT company took place on March, 27 th in Torino. We got many informations on software & hardware aspects: Date pattern decoding Readout ‘triggering’ Oscillator choice Sinus  square signals conversion VHDL code for signal reception The 1 st prototype of PCI board + O/E converter board is under completion. GPS distribution system

15. OPERA TT MEETING BRUSSELS, April 11, 2003 Optical fiber from the master clock PLX 9080 APEX 20KE EEPROM Hot Link 923 Hot Link 933 TX1 HFBR1116T RX1 HFBR2116T EPC2 PECL Local bus To the station RX2 HFBR2116T 10Mhz 5.10E-11 OC-050 Vectron Int. Master clock date Optical fiber to the O/E converter of SM1 & SM2 Data+clock mixed Optical fiber From the SM1 Optical fiber From the SM2 Inputs from GPS receiver (pps, 10Mhz, analog Irig B, digital Irig B) O/E Converter Optional for Lab tests TX2 HFBR1116T Propagation time measurement (optional) GPS distribution system