1. Chapter Four Combinational Logic 1

2. Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2 n distinct elements of coded information. D ECODERS A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. If the n-bit coded information has unused combinations, the decoder may have fewer than 2 n outputs. 2

3. D ECODERS Extract “ Information ” from the code n -to- m line decoder ( n inputs, m <= 2 n output) Binary Decoder Example: 2-bit Binary Number Binary Decoder x1x0 x1x0 Only one lamp will turn on 0000 10001000 3

4. D ECODERS 2-to-4 Line Decoder I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 1 0 0 0 0 10 1 0 0 1 00 0 1 0 1 0 0 0 1 BinaryDecoder I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3 21202120 4

5. D ECODERS 3-to-8 Line Decoder (Binary to Octal conversion) BinaryDecoder xyz xyz D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7 2 222120222120 5

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7. D ECODERS “ Enable ” Control BinaryDecoder 2120E2120E Y0Y1 Y2Y3 Y0Y1 Y2Y3 EI 1 I 0 Y 0 Y 1 Y 2 Y 3 0x 0 0 10 1 0 0 0 10 10 1 0 0 11 00 0 1 0 11 0 0 0 1 I1I0 I1I0 7

8. D ECODERS Expansion A 2 A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 00 0 0 0 0 0 0 1 0 0 10 0 0 0 0 0 1 0 0 1 00 0 0 0 0 1 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 1 0 0 0 0 1 0 10 0 1 0 0 0 0 0 1 1 00 1 0 0 0 0 0 0 1 1 11 0 0 0 0 0 0 0 3 x8 decoder constructed with two 2 x 4 decoders 8

9. 9 4 x16 decoder constructed with two 3 x 8 decoders

10. D ECODERS Active-High / Active-Low I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 1 0 0 0 0 10 1 0 0 1 00 0 1 0 1 0 0 0 1 I 1 I 0 Y 0 Y 1 Y 2 Y 3 0 0 1 1 1 0 11 0 1 1 1 01 1 0 1 1 1 1 1 0 BinaryDecoder I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3 21202120 I1I0 I1I0 Y0Y1 Y2Y3 Y0Y1 Y2Y3 21202120 10

11. I MPLEMENTATION U SING D ECODERS Each output is a minterm All minterms are produced Sum the required minterms Example: Full Adder S ( x, y, z ) = ∑(1, 2, 4, 7) C ( x, y, z ) = ∑(3, 5, 6, 7) x y z C S 0 0 00 0 0 10 1 0 1 00 1 0 1 11 0 1 0 00 1 1 0 11 0 1 1 01 0 1 1 11 11

12. A function with a long list of minterms requires an OR gate with a large number of inputs. If the number of minterms in the function is greater than 2 n /2, then F’ can be expressed with fewer minterms. So we use a NOR gate to sum the minterms of F’. The output of NOR gate complements this sum and generates the normal output F. 12

13. I MPLEMENTATION U SING D ECODERS WITH NAND GATES Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Decoder xyz xyz S C 2 222120222120 13

14. E NCODERS ( EX. K EYBOARD ENCODER ) Perform the inverse operation of a decoder Inputs <= 2 n, n outputs Put “ Information ” into code (it generates the binary code corresponding to the input value). Binary Encoder x 0 x 1 x 2 x 3 y 1 y 0 1 0 0 00 0 1 0 00 1 0 0 1 01 0 0 0 0 11 Only one switch should be activated at a time Binary Encoder y1y0 y1y0 x 0 x 1 x 2 x3 Example: 4-to-2 Binary Encoder 14

15. E NCODERS Octal-to-Binary Encoder (8-to-3) I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 Y 2 Y 1 Y 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 0 00 1 0 0 0 0 0 1 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 1 0 0 0 0 01 0 1 0 1 0 0 0 0 0 01 1 0 1 0 0 0 0 0 0 01 1 1 BinaryEncoder Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0 Limitation: 1- Only one of the input is allowed to be 1 2- When all inputs are zeros, the output is zero but this situation is the same as input Y0=1!! 15

16. P RIORITY E NCODERS 4-Input Priority Encoder ( V is a valid bit indicator) PriorityEncoder VyxVyx D3D2 D1D0D3D2 D1D0 V: is the valid bit indicator that is set to 1 when one or more inputs are equal to 1. 16

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19. E NCODER / D ECODER P AIRS Y2Y1Y0Y2Y1Y0 I7I6 I5I4I3I2 I1I0 I7I6 I5I4I3I2 I1I0 I2I1I0 I2I1I0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Y7Y6 Y5Y4Y3Y2 Y1Y0 Binary Encoder Binary Decoder 19

20. M ULTIPLEXERS (D ATA S ELECTOR ) It Selects binary information from one of many input lines and directs it to a single output line. (Ex. single data bus is required to carry two or more different digital signals) ( 2 n input lines and n selection lines) S 1 S 0 Y 0 I0I0 0 1I1I1 1 0I2I2 1I3I3 MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 01 2301 23 20

21. 21 2-to-1 MUX

22. M ULTIPLEXERS 4-to-1 MUX MUX Y I0I1 I2I3I0I1 I2I3 S 1 S 0 01 2301 23 22

23. M ULTIPLEXERS Quad 2-to-1 MUX A0A1A2A3 A0A1A2A3 B0B1B2B3 B0B1B2B3 MUX Y0 0101 S MUX Y1 0101 S MUX Y2 0101 S MUX Y3 0101 S S MUX A0A1 A2A3A0A1 A2A3 S E Y0Y1 Y2Y3Y0Y1 Y2Y3 B0B1 B2B3B0B1 B2B3 (two 4-bits input, one 4-bits output) 23

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25. I MPLEMENTATION U SING M ULTIPLEXERS MUX Y 01 2301 23 S 1 S 0 x y zF 0 0 00 0 0 11 0 1 01 0 1 10 1 0 00 1 0 10 1 1 01 1 1 11 Any Boolean function of n-variables can be implemented using a MUX with n-1 selection lines Example F ( x, y, z ) = ∑(1, 2, 6, 7) x y F F = z z z F = 0 0 F = 1 1 25

26. MUX Y 01 2345 6701 2345 67 S 2 S 1 S 0 I MPLEMENTATION U SING M ULTIPLEXERS A B C DF 0 0 0 0 0 0 11 0 0 1 00 0 0 1 11 0 1 0 01 0 1 0 0 1 1 00 0 1 1 10 1 0 0 00 1 0 0 10 1 0 0 1 0 1 11 1 1 0 01 1 1 0 11 1 1 1 01 1 1 1 Example F ( A, B, C, D ) = ∑(1, 3, 4, 11, 12, 13, 14, 15) A B C F F = D D D D F = 0 0 F = D F = 1 0 D 1 1 26

27. Y I0I1 I2I3I4I5 I6I7I0I1 I2I3I4I5 I6I7 S 2 S 1 S 0 M ULTIPLEXER E XPANSION 8-to-1 MUX using Dual 4-to-1 MUX & one 2x1 Mux MUX Y 01 2301 23 S 1 S 0 MUX Y 01 2301 23 S 1 S 0 MUX Y 0101 S 0 1 27

28. 28 / 65 D E M ULTIPLEXERS A circuit that receives information from a single line and directs it to one of 2 n possible output lines DeMUX I Y3Y2Y1Y0Y3Y2Y1Y0 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y0 0 000I 0 100I0 1 00I00 1 I000

29. D E M ULTIPLEXERS / D ECODERS BinaryDecoder I1I0E I1I0E Y0Y1 Y2Y3 Y0Y1 Y2Y3 EI 1 I 0 Y 3 Y 2 Y 1 Y 0 0x 0 0 10 0 0 0 1 10 10 0 1 0 11 00 1 0 0 11 1 0 0 0 DeMUX I Y0Y1Y2Y3Y0Y1Y2Y3 S 1 S 0 Y 3 Y2Y2 Y1Y1 Y0Y0 0 000I 0 100I0 1 00I00 1 I000 29

30. 30 T HE P ROBLEMS : 4.1, 4.2, 4.4, 4.13, 4.21, 4.23, 4.25, 4.27, 4.31, 4.33, 4.34, 4.35(a)