Altera University Program Cyclone V SoC Course

Altera University Program Cyclone V SoC Course
Blair Fort

About the Presenter (me)
Ph.D. candidate at the University of Toronto High-Level Synthesis as part of the LegUp group Member of the Altera University Program since 2006 Course materials and exercises Altera Monitor Program

About the University Program Staff
Members: Prof. Stephen Brown Prof. Zvonko Vranesic Kevin Nam Aja Canyon Blair Fort Successful books in print

Why Teach Students about FPGAs?
Field-Programmable Gate Arrays are programmable hardware chips Can be used to implement any digital hardware circuit Digital hardware is found is almost all modern products Consumer produces, like audio and video players Telephone and television equipment Cars, airplanes, trains Medical equipment, and industrial control

Why Teach Students about FPGAs?
Field-Programmable Gate Arrays are programmable hardware chips Can be used to implement any digital hardware circuit Digital hardware is found is almost all modern products Consumer produces, like audio and video players Telephone and television equipment Cars, airplanes, trains Medical equipment, and industrial control FPGAs are … everywhere

About Altera Corporation

High-growth semiconductor company Products include
Altera Highlights Founded in 1983 High-growth semiconductor company Products include FPGAs structured ASICs embedded soft processors design software IP development kits 3,100 employees ~$2 billion in revenue

Altera Products FPGAs: CPLDs: Design Support:
Cyclone series: low cost, high performance Arria series: Mid range, transceivers Stratix series: largest, full featured, highest performance Stratix 10 2X core performance Intel’s 14nm Tri-Gate process 64-bit quad-core ARM Cortex-A53 CPLDs: MAX series: for small, instant-on applications, non-volatile configuration Design Support: Quartus II: easy to use, complete CAD flow Qsys System Integration tool Development environment for embedded systems Nios II: embedded processor, ARM processor Embedded Design Suite: Nios II and ARM

Altera R&D Sites Toronto, Canada St. John’s, Canada Herlev, Denmark
New Device Architectures CAD Algorithms IP University Program St. John’s, Canada Herlev, Denmark High Wycombe, UK San Jose, US Headquarters New Jersey, US Austin, US Penang, Malaysia

Altera University Program Overview

Altera’s University Program Advantage
Ready-to-teach course material for universities Tutorials (written for students, not experienced engineers!) Lab exercises Written by experienced Professors Digital Logic, Computer Organization, Embedded Systems Design examples I.P. cores for all of the peripherals on our teaching boards Prebuilt Nios II and ARM computer systems for use in courses Software: Quartus II, Nios II and ARM development tools Easy to use, powerful tools All software licenses are free to universities Distributed through the Web ( Best-in-class lab boards for teaching

DE1-SoC $150 USD Cyclone V SoC FPGA Dual-core ARM Cortex-A9 FPGA
1GB DDR 3 SDRAM, MicroSD USB, Triple-speed Ethernet ADC, Accelerometer LED, Pushbutton FPGA 85K Programmable Logic Elements 64 MB SDRAM DVD-quality audio in/out, Video in/VGA out PS/2, IrDA 4 debounced pushbuttons, 10 slider switches, 10 red LEDs, six 7-segment displays Expansion headers Built-in USB Blaster for FPGA programming

DE-series Design Objective
Boards are ideal for use across the curriculum: Introductory Digital Logic Computer Organization Embedded Systems Advanced Digital Logic (System Design) Senior Digital Design Projects

Research Platform: DE5-Net (Stratix V)
USB Blaster RJ45 SFP+ x4 PCI Express x8 SW x4 LED x4 7-seg x2 DDR3 SO-DIMM B DDR3 SO-DIMM A SATA x4 QDR II+ SRAM Flash

Getting Started with the U.P.
Enroll as a member Professor at Receive free licenses for Quartus II CAD tools, Nios II processor, and other I.P. core designs Request a free sample DE-series board After evaluating the board: Purchase additional boards (at Altera U.P. prices) from or Request a larger donation (We also offer grants of FPGA chips for teaching & research projects)

Altera U.P. Web Site

Over 1,500 Universities with Altera Labs
Canada 50 Labs Europe 500 Labs United States 450 Labs East Asia 500 Labs

ARM Cortex-A9 Tutorial #1

Designs the ARM range of RISC processor cores
Founded in November 1990 Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers ARM does not fabricate silicon itself Also develop technologies to assist with the designing of the ARM architecture Software tools, boards, debug hardware Application software Bus architectures Peripherals, etc

ARM Cortex Processor (v7) Families
ARM Cortex-A family (v7-A): Applications processors for full OS and 3rd party applications ARM Cortex-R family (v7-R): Embedded processors for real-time signal processing, control applications ARM Cortex-M family (v7-M): Microcontroller-oriented processors for MCU and SoC applications

ARM Cortex Processor (v7) Highlights
Reduced Instruction Set Computer (RISC) architecture aka. Load/Store architecture 16 and 32-bit instruction modes ARM (32-bits) Thumb (16-bits) Thumb 2 (16/32-bits) 32-bit word-length 16 general-purpose registers Condition code flags, usable with many types of instructions

Cyclone V SoC and Arria V SoC families
ARM Cortex-A9 Cyclone V SoC and Arria V SoC families 1-2 Cores Application-level processor Features: 800 MHz 32-bit processor 32 KB instruction and data L1 caches Snoop control unit (SCU) Accelerator Coherency Port (ACP) Unified 512KB L2 Cache ARM NEON™ single instruction, multiple data (SIMD) coprocessor Floating point unit

ARM Cortex-A9 MPCore CPU 0 CPU 1 ARM Cortex-A9 ARM Cortex-A9
SIMD and FPU SIMD and FPU MMU MMU I-Cache D-Cache I-Cache D-Cache Private Timers Private Timers Generic Interrupt Controller Accelerator Coherency Port and Snoop Controller

ARM Cortex-A9 Registers
Arguments and Result Register variables Must be preserved Scratch register Stack Pointer Link Register Program Counter This is defined by the Procedure Call Standard for the ARM Architecture (AAPCS) Link register stores the return address for subroutine calls R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 / SP R14 / LR R15 / PC

Interrupt disable bits
ARM Cortex-A9 CPSR Current Program Status Register (CPSR) 31 30 29 28 7 6 5 4 N Z C V I F T Condition code flags Processor mode ARM or Thumb operation Interrupt disable bits

Unified Assembler Language (UAL)
ARM Instruction Set 32-bit instructions Unified Assembler Language (UAL) Common syntax for ARM and Thumb instructions Instruction Classes Branch instructions Data-processing instruction Load and store instructions Status register access instructions Miscellaneous instructions

ARM Machine Code Format
Rd: Destination register Rn: Operand 1 Operand 2 12-bit immediate offset or Rm (lower four bits) and shift_operand Condition codes For conditional execution of the instruction 31 28 27 20 19 16 15 12 11 Condition OP code Rn Rd Immediate or Rm

ARM Assembly Syntax Operand 2: 12-bit immediate Operand 2: register
Operation Result, Operand 1, Operand 2 Operand 2: 12-bit immediate OP Rd, Rn, #value Operand 2: register OP Rd, Rn, Rm Operand 2: register with shift OP Rd, Rn, Rm, SHIFT #shift_value SHIFT: left/right shift or rotate 5-bit shift value Changes contents of Rm prior to being used 31 28 27 20 19 16 15 12 11 Condition OP code Rn Rd Immediate or Rm

Branch Instructions Branch target address Syntax
Program Counter (pc/r15) + 24-bit offset (2’s complement) Syntax B{condition code} LABEL BEQ LOOP 31 28 27 24 23 Condition OP code Offset or Rm

Branch Instructions Branch target address Syntax Subroutine calls
Program Counter (pc/r15) + 24-bit offset (2’s complement) Syntax B{condition code} LABEL BEQ LOOP Subroutine calls Branch and Link instruction: BL LABEL Next address is stored in LR, for return Subroutine returns Branch and Exchange: BX LR 31 28 27 24 23 Condition OP code Offset or Rm

ARM Condition Codes

Data-processing Instructions
Arithmetic ADD, SUB, MUL, MLA (multiple accumulate) Logic AND, ORR, EOR BIC (bit clear), TST (test) Move MOV, MVN (move negative (not)), MOVT (move top) Shift and rotate ASR, LSL, LSR, ROR Comparison CMP, CMN (compare negative) 31 28 27 20 19 16 15 12 11 Condition OP code Rn Rd Immediate or Rm

Setting Condition Codes
Always set by comparison and test instructions Arithmetic, logic and move instruction can optionally affect the flags. ADD R2, R3, R4 (does not affect the flags) ADDS R2, R3, R4 (does affect the flags)

Conditional Execution
Most ARM instructions are executed conditionally. ADD R2, R3, R4 (always execute) ADDAL R2, R3, R4 ADDNE R2, R3, R4 (execute only if the Z flag is clear)

Most ARM instructions are executed conditionally. ADD R2, R3, R4 (always execute) ADDAL R2, R3, R4 ADDNE R2, R3, R4 (execute only if the Z flag is clear) Example: c = (a > b) ? (a – b) : (b – a);

Most ARM instructions are executed conditionally. ADD R2, R3, R4 (always execute) ADDAL R2, R3, R4 ADDNE R2, R3, R4 (execute only if the Z flag is clear) Example: c = (a > b) ? (a – b) : (b – a); START: CMP R0, R1 BLT LESS SUB R2, R0, R1 B END LESS: SUB R2, R1, R0 END:

Most ARM instructions are executed conditionally. ADD R2, R3, R4 (always execute) ADDAL R2, R3, R4 ADDNE R2, R3, R4 (execute only if the Z flag is clear) Example: c = (a > b) ? (a – b) : (b – a); START: CMP R0, R1 START: CMP R0, R1 BLT LESS SUBGT R2, R0, R1 SUB R2, R0, R1 SUBLE R2, R1, R0 B END LESS: SUB R2, R1, R0 END:

Directives provide information required by the assembler
Assembler Directives Directives provide information required by the assembler GNU Assembler directives .text Identifies code section .global symbol Makes symbol visible outside the assembled object file .word expressions Comma separated expression are assembled into 32-bit numbers .end Marks the end of the source file

Hands-on Session 1 Create a software project targeting the ARM Cortex-A9 Compile the application Download the compiled software to the DE1-SoC Run and debug the application

Exercise 1: Greatest Common Divisor (GCD)
int a = 54, b = 24; do { if ( a > b) a = a – b; else b = b – a; } while (a != b);

Exercise 1: Greatest Common Divisor (GCD)
int a = 54, b = 24; do { if ( a > b) a = a – b; else b = b – a; } while (a != b); .text .global _start _start: MOV R0, #54 /* Register R0 is the first number. */ MOV R1, #24 /* Register R1 is the second number. */ GCD: CMP R0, R1 /* Set the condition codes. */ SUBGT R0, R0, R1 /* If (R0 > R1) then R0 = R0 - R1. */ SUBLT R1, R1, R0 /* If (R0 < R1) then R1 = R1 - R0. */ BNE GCD /* If (R0 != R1) then loop again. */ STOP: B STOP /* If (R0 == R1) then stop. */ .end

Step 1: Start Altera Monitor Program

Step 2: Create a New Project
Sets up the Altera Monitor Program Select files to work with Specify target system

Step 2.1: Specify name, directory and architecture

Step 2.2: Select the ARM Cortex-A9 System

Step 2.3: Select Program Type

Step 2.4: Add Source File

Step 2.5: Set Board Connection and Select Processor

Step 2.6: Leave Default Memory Settings

Step 3: Compile and Load Compile your assembly language program Load the compiled code into the memory on the DE1-SoC board

Step 4: Disassembly Window

Registers

Info & Error Msgs

Terminal

Step 5: Single Step your Program

Step 6: Change Register View

Step 7: Single Step your Program Again

Step 8: Set a Breakpoint

Step 9: Run to the Breakpoint

Step 10: Change Register View

Interrupt disable bits
Step 11: Look at CPSR 31 30 29 28 7 6 5 4 N Z C V I F T Condition code flags Processor mode ARM or Thumb operation Interrupt disable bits

Step 11: Look at CPSR CPSR = 0x200001D3 31 30 29 28 7 6 5 4 N Z C V I
CPSR = 0x200001D3 N Z C V I F T

Step 11: Look at CPSR CPSR = 0x200001D3 31 30 29 28 7 6 5 4 N Z C V I
CPSR = 0x200001D3 N Z C V I F T 1

What should have happened in our code?
Step 11: Look at CPSR 31 30 29 28 7 6 5 4 CPSR = 0x200001D3 What should have happened in our code? N Z C V I F T 1 GCD: CMP R0, R1 SUBGT R0, R0, R1 SUBLT R1, R1, R0 BNE GCD

What should have happened in our code?
Step 11: Look at CPSR 31 30 29 28 7 6 5 4 CPSR = 0x200001D3 What should have happened in our code? Note GT is Z clear and N equals V LT is N is not equal to V NE is Z clear N Z C V I F T 1 GCD: CMP R0, R1 SUBGT R0, R0, R1 SUBLT R1, R1, R0 BNE GCD

Step 12: Set a Breakpoint at the End and Run

Step 13: Restart the Program

Step 14: Single Step

Step 15: Modify R0

Step 16: Run to Breakpoint

Step 17: Disconnect from the DE1-SoC Board

Load and Store Instructions
Reading data from memory How do we read the memory contents at address 0x40 into register R1 … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0x40 into register R1 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0x40 into register R1 MOV R0, #0x40 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0x40 into register R1 MOV R0, #0x40 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x40 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0x40 into register R1 MOV R0, #0x40 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x40 0x 0x R1 0x … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0xFF200040 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0xFF200040 LDR R1, [R0] 0xFF is larger than 16 bits … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0x0040 MOVT R0, #0xFF20 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0x0040 MOVT R0, #0xFF20 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x40 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0x0040 MOVT R0, #0xFF20 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0xFF200040 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 MOV R0, #0x0040 MOVT R0, #0xFF20 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0xFF200040 0x 0x R1 0xFEDCBA90 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 LDR R0, =0xFF200040 LDR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 LDR R0, =0xFF200040 LDR R1, [R0] Assembled code: LDR R0, [pc, #0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0xFF200040 0x 0x

Reading data from memory How do we read the memory contents at address 0xFF into register R1 LDR R0, =0xFF200040 LDR R1, [R0] Assembled code: LDR R0, [pc, #0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0xFF200040 0x 0x Literal Pool

Writing data to memory How do we write the contents of R1 to the memory location 0x40 LDR R0, =0x STR R1, [R0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x 0x

Writing data to memory How do we write the contents of R1 to the memory location 0x40 LDR R0, =0x STR R1, [R0] Assembled code: LDR R0, [pc, #0] … 0xFF200040 0xFEDCBA90 … R0 0x 0x R1 … 0x 0x 0x 0x

Addressing Modes Register indirect: Offset mode: Register offset: [Rn]
Immediate offset: [Rn, #offset] Register offset: [Rn, ± Rm, shift]

Addressing Modes Register indirect: Offset mode: Indexed mode:
Register offset: [Rn] Offset mode: Immediate offset: [Rn, #offset] Register offset: [Rn, ± Rm, shift] Indexed mode: Updates the contents of Rn

Addressing Modes Register indirect: Offset mode: Indexed mode:
Register offset: [Rn] Offset mode: Immediate offset: [Rn, #offset] Register offset: [Rn, ± Rm, shift] Indexed mode: Updates the contents of Rn Pre-indexed mode: Immediate offset: [Rn, #offset]! Register offset: [Rn, ± Rm, shift]! Post-indexed mode: Immediate offset: [Rn], #offset Register offset: [Rn], ± Rm, shift

Storing and Loading Multiple Registers
Two pseudo-instructions PUSH and POP For storing and loading multiple registers

Two pseudo-instructions PUSH and POP For storing and loading multiple registers PUSH {R1, R3-R5} POP {R1, R3-R5}

Two pseudo-instructions PUSH and POP For storing and loading multiple registers PUSH {R1, R3-R5} STMDB SP!, {R1, R3-R5} POP {R1, R3-R5} LDMIA SP!, {R1, R3-R5}

Exercise 2: Dot product

Step 3: Notice the use of the Literal Pool

Step 4: Go to the Memory Window

Step 5: Find the Address of AVECTOR

Step 6: Find the Address of BVECTOR

Step 7: Find the Data of the Vectors

Step 8: Change to Signed Representation

Step 9: Change to Decimal Format

Step 10: Find Literal Pool in the Disassembly Window

Step 11: Single Step or Set Breakpoints and Run

Step 12: Final Result in R3

Step 12: … And in the Memory Location DOTP

Where did we go from here?
Summary #1 What did we learn? ARM Cortex-A9 Unified Assembly Language (UAL) How to run and debug programs using the Altera Monitor Program Where did we go from here? Tutorials: Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM Literature: ARM Architecture Reference Manual

Intro to Cyclone V’s Hard Processor System (HPS)
Tutorial #2

ARM Cortex-A9 MPCore CPU 0 CPU 1 ARM Cortex-A9 ARM Cortex-A9
SIMD and FPU SIMD and FPU MMU MMU I-Cache D-Cache I-Cache D-Cache Private Timers Private Timers Generic Interrupt Controller Accelerator Coherency Port and Snoop Controller

Altera HPS Block Diagram
MPCore

4 GB HPS MPCore 3 GB L2 Cache 2 GB 1 GB 0 GB

4 GB HPS MPCore 3 GB L2 Cache L3 Interconnect 2 GB 1 GB 0 GB

4 GB HPS MPCore 3 GB Boot ROM L2 Cache 2 GB 1 GB Boot Region 0 GB

4 GB HPS MPCore 3 GB SDRAM Window Boot ROM L2 Cache 2 GB SDRAM Controller 1 GB DDR3 Chips Boot Region 0 GB

4 GB HPS MPCore 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB SDRAM Controller 1 GB DDR3 Chips Boot Region 0 GB

4 GB HPS MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB SDRAM Controller 1 GB DDR3 Chips Boot Region 0 GB

4 GB HPS MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB GPIO SDRAM Controller 1 GB LEDG KEY DDR3 Chips Boot Region 0 GB

4 GB HPS MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

4 GB HPS Peripherals MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

Hands-on Session 2 Write a program that uses HPS peripherals Write a program that uses FPGA peripherals Write a program that uses printf and scanf

Exercise 3: HPS Peripherals
The program will use the HPS pushbutton and LED

Both are attached to the memory-mapped GPIO 1 port
HPS Pushbutton and LED Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers Data, Interrupts, Configuration, etc. Data Register Direction Register Interrupt Enable … External Port …

HPS Pushbutton and LED Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers Data, Interrupts, Configuration, etc. Each bit corresponds to a different I/O pin Data Register Direction Register Interrupt Enable … External Port …

HPS Pushbutton and LED Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers Data, Interrupts, Configuration, etc. Each bit corresponds to a different I/O pin LED Bit 24 Data Register Direction Register Interrupt Enable … External Port …

HPS Pushbutton and LED Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers Data, Interrupts, Configuration, etc. Each bit corresponds to a different I/O pin LED Bit 24 Pushbutton Bit 25 Data Register Direction Register Interrupt Enable … External Port …

Read the pushbutton and display the value on the LED
Program Read the pushbutton and display the value on the LED #define bit_25_pattern 0x int main(void)( volatile int * HPS_GPIO1_Data = (int *) 0xFF709000; volatile int * HPS_GPIO1_Direction = (int *) 0xFF709004; volatile int * HPS_GPIO1_External = (int *) 0xFF709050; *HPS_GPIO1_Direction = (1 << 24); // Set bit 24 (LEDG) of GPIO1 // to be an output while(1) { int value = *HPS_GPIO1_External; // Read the value of the GPIO port value &= bit_25_pattern; // Mask out the pushbutton value *HPS_GPIO1_Data = (value >> 1); // Set the LEDG to the read value }

Step 2: Compile and Load Compile your C language program Load the compiled code into the memory on the DE1-SoC board

Step 3: Go to the Memory Window

Step 4: Jump to the GPIO’s Address Range

Step 5: Why is the Memory Window Blank?

Step 6: Highlight the First Two Registers of the GPIO Port

Step 7: Right Click and Read Selected Address Range

Step 8: Read the GPIO’s External Port

Step 9: Hold Down the Button and Re-read the Location

Step 11: Jump to Main

Step 12: Set a Breakpoint and Run to Main

Step 13: Single Step or Run

Step 14: Stop while Holding Down the Pushbutton

How About Communication with the FPGA?
4 GB HPS FPGA Peripherals MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

There are Several Bridges Between the HPS and FPGA
4 GB HPS FPGA Peripherals MPCore Timers 3 GB SDRAM Window On-Chip RAM Boot ROM L2 Cache Bridges 2 GB Ports GPIO SDRAM Controller 1 GB USB Ethernet LEDG KEY DDR3 Chips Boot Region 0 GB

HPS-to-FPGA Bridge 4 GB HPS FPGA Peripherals MPCore FPGA Slave Region
Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache H2F 2 GB Ports GPIO SDRAM Controller Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Lightweight HPS-to-FPGA Bridge
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache LW H2F 2 GB Ports GPIO SDRAM Controller Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Exercise 4: FPGA Peripherals
Circuit must be configured in the FPGA

Pre-built DE1-SoC Computer System
Download the system onto the DE1-SoC board Can be configured to load on power-up Develop programs using the Altera Monitor Program

Exercise 4: FPGA Peripherals
We will use the red LEDs, seven-segment display and the slider switches In the DE1-SoC, they are connecting to the Lightweight HPS-to-FPGA bridge using the Altera Parallel I/O (PIO) component

Parallel I/O (PIO) Component
PIO Components Parallel I/O (PIO) Component Depending on the PIO’s settings, not are registers are usable Data Register Direction Register Interruptmask Register Edgecapture Register …

Parallel I/O (PIO) Component
PIO Components Parallel I/O (PIO) Component Depending on the PIO’s settings, not are registers are usable DE1-SoC Computer Red LEDs Base address: 0xFF200000 Seven segment displays Base address: 0xFF200020 Slider switches Base address: 0xFF200040 Data Register Direction Register Interruptmask Register Edgecapture Register …

Read switches and display on LEDs and 7-Segs
Program Read switches and display on LEDs and 7-Segs int main(void)( volatile int * LEDs = (int *) 0xFF200000; volatile int * HEX3_HEX0 = (int *) 0xFF200020; volatile int * SW_switch = (int *) 0xFF200040; int hex_conversions[16] = {0x3F, ..., 0x71}; while(1) { int value = *SW_switch; *LEDs = value; int first_digit = value & 0xF; int second_digit = (value >> 4) & 0xF; int third_digit = (value >> 8) & 0xF; int hex_value = hex_conversions[first_digit]; hex_value |= hex_conversions[second_digit] << 8; hex_value |= hex_conversions[third_digit] << 16; *HEX3_HEX0 = hex_value; }

Step 1.2: Select the DE1-SoC Computer System

Step 2: Program the FPGA with the Computer System

Step 4: Jump to the FPGA’s Address Range

Step 5: Read the Switches, LEDs and 7-Segs Locations

Step 6: Toggle Some Switches and Re-read

Step 7: Write Some Values to the LEGs and 7-Segs

Step 8: Go to the Main Function

Step 9: Set a Breakpoint at the Load from Switches

Step 10: Toggle Some Switches and then Single Step

Step 11: Single Step until the LEDs are Set

Step 12: Single Step or Run

Can FPGA Components access the HPS Memory?
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache Bridges 2 GB Ports GPIO SDRAM Controller Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. Boot Region 0 GB

Yes, by using the FPGA to HPS bridge.
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache F2H 2 GB Ports GPIO SDRAM Controller Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. 0 GB

What about the MPCore’s Cached Data?
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB SDRAM Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache F2H 2 GB Ports GPIO SDRAM Controller Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. 0 GB

Accelerator Coherency Port (ACP)
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB ACP Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache ACP F2H 2 GB Ports GPIO SDRAM Controller Ports SDRAM Window 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. 0 GB

What if the FPGA Requires Access to the SDRAM?
4 GB HPS FPGA Peripherals MPCore FPGA Slave Region Timers 3 GB ACP Window On-Chip RAM Boot ROM On-Chip Cores L2 Cache Bridges 2 GB Ports GPIO SDRAM Controller Ports SDRAM Window 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. 0 GB

FPGA to SDRAM Direct Access
4 GB HPS FPGA SDRAM MPCore Timers 3 GB On-Chip RAM Boot ROM On-Chip Cores L2 Cache Bridges 2 GB Ports GPIO SDRAM Controller SDRAM Ports 1 GB USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc. 0 GB

Exercise 5: Semihosting
Virtual Operating System Allows C programs to make system calls I/O functions Time functions File operations Altera Monitor Program supports a subset printf and scanf to and from the terminal window. Some time functions

Printf, scanf and time functions
Program Printf, scanf and time functions #include <stdio.h> #include <time.h> int main(void)( char str[64]; int age = 0; // Get the initial timestamp clock_t start_time = clock(); while(1){ printf("What is your name?\n"); scanf("%s",str); printf("What is your age?\n"); scanf("%d",&age); ... } return 0;

Step 1.3: Select Program Type and Sample Program

Step 1.4: Automatically Includes Example’s Source Files

Step 4: Run

Step 5: Type in your name

Step 6: Type in your age

Step 7: See the Result of the Semi-hosting Functions

Typical ARM Cortex-A9 Boot Sequence
Boot ROM Hard coded by Altera Determines the boot source by reading the boot select pins Preloader In Flash/SD Card or FPGA Typically initializes the DDR3 SDRAM and HPS I/O pins Boot loader Loads and starts the operating system

Boot Sequence with Altera Monitor Program
Resets the HPS Halts the code in the Boot ROM Loads a preloader into the HPS on-chip RAM Preloader comes pre-compiled with the Monitor Program Initializes the DDR3 SDRAM and HPS I/O pins Enables the HPS-FPGA bridges Disables the watchdog timers Re-maps the DDR3 SDRAM to address 0x Loads the user’s code into the DDR3 SDRAM Pauses the processor at the first instruction

Summary #2 What did we learn? Altera HPS peripherals Memory layout of the HPS How to communicate between the HPS and FPGA ARM Cortex-A9 Boot Sequence Where did we go from here? Tutorials: Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM DE1-SoC Computer System Literature: Cyclone V Handbook Address Map for HPS

ARM’s Generic Interrupt Controller
Tutorial #3

Processor Modes ARM processor modes
User Non-privileged execution (user programs) Supervisor (SVC) 1 Privileged execution (OS code) Abort Error condition mode Undefined Undefined instruction fetched System “Same” as Supervisor IRQ 2 Interrupt mode FIQ Fast interrupt mode Monitor Secure mode (only for “security extensions”) The ARM A9 is in SVC mode after being reset IRQ mode is entered when a hardware interrupt occurs

Current Program Status Register
The Current Program Status Register (CPSR) includes mode bits: writing to these bits can change the mode Processor mode: (User), (FIQ), (IRQ), (SVC), 10111 (Abort), (Undefined), (System)

ARM Banked Registers for each Mode
Separate copies exist of some registers in each mode Each mode has a unique SP and LR SPSR is a saved copy of previous CPSR

Processor mode can be changed manually
Modes and Exceptions Processor mode can be changed manually MOV R1, #0x12 // mode bit pattern for IRQ mode MSR CPSR, R1 // change to IRQ mode Processor mode can be changed due to an exception Reset of the ARM processor Error conditions fetched an unimplemented instruction unaligned word read/write unaligned instruction fetch Execution of the SVC instruction causes an exception External hardware interrupt

Exception Processing main: instruction … Exception
The ARM processor automatically: Saves CPSR into banked SPRS Saves return address into banked LR Changes CPSR to reflect the Exception Mode Fetches instruction from exception vector table

Exception Vector Table
Address Exception Priority Mode entered 0x0 Reset 1 SVC 0x4 Unimplemented instruction 6 Undefined 0x8 SVC instruction - 0xC Data access violation 2 Abort 0x10 Instruction access violation 5 0x18 Interrupt 4 IRQ 0x1C Fast interrupt 3 FIQ

Returning from an Exception
The LR is “related” to the return address: Example: SUBS PC, LR, #4 // returns from IRQ handler Note: SUBS with destination PC means “return from exception”. It causes SPSR to be restored back into CPSR! Processor mode Return address Data Abort LR-8 IRQ, FIQ, pre-fetch Abort LR-4 SVC instruction LR Undefined instruction

Exception Vector Table (Assembly code)
.section .vectors, “ax” B _start // reset vector B SERVICE_UND // undefined instruction vector B SERVICE_SVC // software interrrupt vector B SERVICE_ABT_INST // aborted prefetch vector B SERVICE_ABT_DATA // aborted data vector .word 0 // unused vector B SERVICE_IRQ // IRQ interrupt vector B SERVICE_FIQ // FIQ interrupt vector .text Main: … … SERVICE_IRQ: // code for handling the IRQ exception goes here SUBS PC, LR, #4 // return from IRQ mode

Exception Handlers (and Vectors) in C code
// Define the IRQ exception handlers void __attribute__ ((interrupt)) __cs3_reset (void) { … } void __attribute__ ((interrupt)) __cs3_isr_undef (void) { … } void __attribute__ ((interrupt)) __cs3_isr_swi (void) { … } void __attribute__ ((interrupt)) __cs3_isr_pabort (void) { … } void __attribute__ ((interrupt)) __cs3_isr_dabort (void) { …} void __attribute__ ((interrupt)) __cs3_isr_irq (void) { code for handling the IRQ exception goes here … } void __attribute__ ((interrupt)) __cs3_isr_fiq (void) { … } The C compiler and linker will automatically make the exception vector table

ARM Interrupt Architecture
A9 Core A9 Core IRQ IRQ Peripheral IRQ Generic Interrupt Controller (GIC) Peripheral IRQ … … Peripheral IRQ Various peripherals, MMU, etc. GIC: handles up to 255 interrupt sources; sends IRQ to either/both A9 Cores

Generic Interrupt Controller (GIC)
PPI: private peripheral interrupt (IRQ for a specific processor) SPI: share peripheral interrupt (IRQ for either processor) SGI: software generated interrupt (IRQ caused by writing to a special register in the GIC

Interrupt IDs Each peripheral is assigned an interrupt ID DE1-SoC Computer Interrupt IDs:

GIC Example Pushbutton KEY IRQ 73 (ID 73) KEY interrupt signal is received by Distributor. If ID 73 is enabled for CPU 0, send to CPU Interface 0, which can send to A9 core

Summary of Interrupt-driven Code
Set up vector table Main program initializes SP for IRQ mode, initializes GIC for each interrupt ID, initializes peripherals (like KEY port), enables interrupts on A9 processor (CPSR bit I = 0), then loops Exception handler for IRQ Queries GIC to find the interrupt ID Calls the appropriate interrupt service routine (ISR) Returns from exception (SUBS PC, LR, #4) Interrupt Service Routine (ISR) Clears interrupt source Performs interrupt function

Exercise 6: Handling Interrupts
We will look at the code required for handling interrupts generated by the FPGA’s pushbutton keys 1. Assembly code 2. C code

Handling Interrupts: Assembly Code
Step 1: Set up vector table .section .vectors, "ax" B _start // reset vector B SERVICE_UND // undefined instruction vector B SERVICE_SVC // software interrrupt vector B SERVICE_ABT_INST // aborted prefetch vector B SERVICE_ABT_DATA // aborted data vector .word 0 // unused vector B SERVICE_IRQ // IRQ interrupt vector B SERVICE_FIQ // FIQ interrupt vector

Step 2: Set stack pointers /* Set up stack pointers for IRQ and SVC processor modes */ MOV R1, #INT_DISABLE | IRQ_MODE MSR CPSR_c, R1 // change to IRQ mode LDR SP, =A9_ONCHIP_END - 3 // set IRQ stack to top of A9 onchip memory /* Change to SVC (supervisor) mode with interrupts disabled */ MOV R1, #INT_DISABLE | SVC_MODE MSR CPSR, R1 // change to supervisor mode LDR SP, =DDR_END - 3 // set SVC stack to top of DDR3 memory

Step 2: Enable interrupts /* To configure the FPGA KEYS interrupt (ID 73): * 1. set the target to cpu0 in the ICDIPTRn register (addr 0xFFFED848) * 2. enable the interrupt in the ICDISERn register (addr 0xFFFED108) */ LDR R0, =0xFFFED848 // ICDIPTRn: processor targets register LDR R1, =0x // set targets to cpu0 STR R1, [R0] LDR R0, =0xFFFED108 // ICDISERn: set enable register LDR R1, =0x // set interrupt enable ...

Step 3: Exception Handler SERVICE_IRQ: PUSH {R0-R7, LR} /* Read the ICCIAR from the CPU interface */ LDR R4, =MPCORE_GIC_CPUIF LDR R5, [R4, #ICCIAR] // read the interrupt ID FPGA_IRQ1_HANDLER: CMP R5, #FPGA_IRQ1 UNEXPECTED: BNE UNEXPECTED // if not recognized, stop here BL KEY_ISR EXIT_IRQ: /* Write to the End of Interrupt Register (ICCEOIR) */ STR R5, [R4, #ICCEOIR] POP {R0-R7, LR} SUBS PC, LR, #

Step 4: Interrupt Service Routine (ISR) KEY_ISR: LDR R0, =KEY_BASE // base address of pushbutton KEY parallel port LDR R1, [R0, #0xC] // read edge capture register MOV R2, #0xF STR R2, [R0, #0xC] // clear the interrupt ... END_KEY_ISR: BX LR

Step 1.6: Choose the Exceptions Memory Settings

Step 4: Notice the Starting Address

Step 5: Look at the Vector Table

Step 6: Look at the Exception Handler

Step 7: Look at the Interrupt Service Routine

Step 8: Set a Breakpoint at the Beginning of the ISR

Step 9: Single Step and Notice the Change of Mode

Step 10: Single Step and Notice the new Stack Pointer

Step 11: Single Step and Notice the Change of Mode

Step 12: Single Step and Notice the new Stack Pointer

Step 13: Run the Program

Step 14: Single Step Through the ISR

Step 15: See the value of the Edge Capture Register

Handling Interrupts: C Language Code
Step 1: Set up vector table // Define the remaining exception handlers void __attribute__ ((interrupt)) __cs3_reset (void) { while(1); } void __attribute__ ((interrupt)) __cs3_isr_undef (void) ...

Step 2: Set stack pointers int stack, mode; // top of A9 onchip memory, aligned to 8 bytes stack = A9_ONCHIP_END - 7; /* change processor to IRQ mode with interrupts disabled */ mode = INT_DISABLE | IRQ_MODE; asm("msr cpsr, %[ps]" : : [ps] "r" (mode)); /* set banked stack pointer */ asm("mov sp, %[ps]" : : [ps] "r" (stack)); /* go back to SVC mode before executing subroutine return! */ mode = INT_DISABLE | SVC_MODE;

Step 2: Enable interrupts /* configure the FPGA KEYs interrupts */ *((int *) 0xFFFED848) = 0x ; *((int *) 0xFFFED108) = 0x ; ...

Step 3: Exception Handler void __attribute__ ((interrupt)) __cs3_isr_irq (void) { // Read the ICCIAR from the processor interface int address = MPCORE_GIC_CPUIF + ICCIAR; int int_ID = *((int *) address); if (int_ID == KEYS_IRQ) // check if interrupt is from the KEYs pushbutton_ISR (); else while (1); // if unexpected, then stay here // Write to the End of Interrupt Register (ICCEOIR) address = MPCORE_GIC_CPUIF + ICCEOIR; *((int *) address) = int_ID; return; }

Step 4: Interrupt Service Routine (ISR) void pushbutton_ISR( void ) { volatile int * KEY_ptr = (int *) KEY_BASE; volatile int * HEX3_HEX0_ptr = (int *) HEX3_HEX0_BASE; int press, HEX_bits; press = *(KEY_ptr + 3); // read the pushbutton interrupt register *(KEY_ptr + 3) = press; // Clear the interrupt ... return; }

Step 1.4: Add C Source File

Step 1.6: Choose the Exceptions Memory Settings

Step 4: Look at the Exception Handler

Step 5: Set a Breakpoint at the Interrupt Service Routine

Step 6: Set a Breakpoint and Run to the Main Function

Step 7: Single Step through Setting the Stack Pointers

Summary #3 What did we learn? Banked registers Generic Interrupt Controller Setting the stack pointers Where did we go from here? Tutorials: Introduction to the ARM Processor Altera Monitor Program Tutorial for ARM DE1-SoC Computer System Literature: Cyclone V Handbook

Creating a Custom FPGA System for ARM
Tutorial #4

What if you want to create a custom system?
HPS FPGA MPCore Timers On-Chip RAM Boot ROM On-Chip Cores L2 Cache Bridges Ports GPIO SDRAM Controller Ports USB Ethernet LEDG KEY DDR3 Chips LEDR Switches Etc.

Quartus II System Integration Tool (Qsys)

Qsys Windows Selected Components And connectivity Available Components
Messages

Select Components to add to the System

Configure the Components using their Wizards

HPS Component: Adding/Removing FPGA to SDRAM Bridges

HPS Component: Editing HPS Peripherals

HPS Component: Editing SDRAM Parameters

Component is now in the System

Creating a Custom System
Select a processor Altera HPS or a Nios II Add off-the-shelf with standard interfaces (SPI, I2C, JTAG, etc.) to help solve the problem Use existing drivers or write one yourself Sometimes an existing driver needs to be augmented for a particular application Add custom components when the needed ones are not available (or too expensive) Add I/O as needed Write code to run on the system Usually a single program

How to put them together?
Qsys system integration tool Add components Quartus II software Synthesize circuit for the FPGA Altera Monitor Program For compiling and debugging software

Hands-on Session 4 Build a system using the Qsys system integration tool Compile the system using the Quartus II software Download the system to the board Run the previous software application

Exercise 7: Making a Custom System
Using Qsys make a system with: Altera HPS component PIO cores for: Red LEDs Seven Segments Displays Slider switches

Step 1: Open the DE1_SoC Project in Quartus II

Step 2: Open the DE1_SoC Project in Quartus II

Step 3: Launch Qsys

Step 4: Select the Computer System

Step 5: The Pre-Started System

Step 6: Add PIO Component for the LEDRs

Step 7: Configure the PIO for the LEDRs

Step 8: Add and Configure a PIO for the 7-Segs

Step 9: Add and Configure a PIO for the Switches

Step 10: Current System

Step 11: Export PIOs’ External Connections

Step 12: Minimize the PIOs

Step 13: Make Connections

Step 14: Go to Address Map Tab

Step 15: Set the Slave Addresses

Step 16: Generate the System

Step 17: Generate the System

Step 18: System Generation Finished

Step 18: Generated System
module Computer_System ( clk_clk, reset_reset_n, // LEDs ledr_export, // Seven Segs hex3_hex0_export, // Slider Switches sw_export, ... ); FPGA LEDs HPS 7-Segs Switches

Step 19: Create Top Level File for project
System must be instantiated in your design Must connect system ports to the I/O ports In this demo the top level file has been created for you Compile your project. Approximately 2 minutes. Open the DE1_SoC.v to examine the system connectivity while Quartus II compiles the project.

Step 20: Compile the System in Quartus II

Step 21: Wait for Compilation to Finish

Step 22.2: Select a Custom System

Step 23: Program the FPGA with the Custom System

Step 25: View Memory Content

Summary #4 What did we learn? How to create a custom system with the Altera HPS component Where did we go from here? Tutorials: Introduction to the Altera Qsys System Integration Tool Making Qsys Components Quartus II Introduction Literature: Quartus II Handbook Volume 1: Section II. System Design with Qsys

Altera University Program Cyclone V SoC Course

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