1. ESCI Base

2. Serial Communication TX RX 8bits Interrupt on Receiver Full 4 Enhanced Serial Communication Interface (eSCI) in the PXR40 eSCIB is used for pins TXD_B and RXD_B connected to the UART interface board eSCI_B_BASE = 0xff9b.4000 Offset Register 0x0000 Baud Rate Register (eSCI_BRR) f TCLK = f MCLK /16*[SBR] f MCLK = 30 MHz 0x0002 Control Register 1 (eSCI_CR1) 0x0004 Control Register 2 (eSCI_CR2) SCI Data Register (ESCI_DR) 0x0008 Interrupt Flag and Status Register 1 (eSCI_IFSR1) 0x000A Interrupt Flag and Status Register 2 (eSCI_IFSR2) //for LIN Pin TXDB in output SIU_PCR[91].R offset 0xf6 Pin RXDB in input SIU_PCR[92].R offset 0xf8

3. Trames possibles

4. Baud Rate Register (eSCI_BRR) Control Register 1 (eSCI_CR1) eSCI_B.CR1.RIE = 0 Receiver Full Interrupt Disable. eSCI_B.CR1.TE = 1 Transmitter enable eSCI_B.CR1.RE = 1 Receiver enable eSCI_B.CR1.PE = 0 Parity bit generation and checking disabled. eSCI_B.CR1.ILT = 0 Idle line detection starts after reception of a low bit. eSCI_B.CR1.R = 0x000C f TCL K = 9600bauds eSCI_BRR.R = 195 eSCI_CR3

5. eSCI_CR1 (et eSCI_BRR) union { /* Control Register 1 */ vuint32_t R; struct { vuint32_t:3; //BRR reserved vuint32_t SBR:13; //BRR baud rate vuint32_t LOOPS:1; vuint32_t:1; vuint32_t RSRC:1; vuint32_t M:1; vuint32_t WAKE:1; vuint32_t ILT:1; vuint32_t PE:1; vuint32_t PT:1; vuint32_t TIE:1; vuint32_t TCIE:1; vuint32_t RIE:1; vuint32_t ILIE:1; vuint32_t TE:1; vuint32_t RE:1; vuint32_t RWU:1; vuint32_t SBK:1; } B; } CR1;

6. Interrupt flag et status register eSCI_IFSR1

7. Data register union { /* Data Register */ vuint16_t R; struct { vuint16_t RN:1; vuint16_t TN:1; vuint16_t ERR:1; vuint16_t:1; vuint16_t RD_11:4; vuint16_t D:8; } B; } DR; /* Legacy naming - refer to SDR in Reference Manual */