1. A Mini Stereo Digital Audio Processor Design DINESH GUNDU VIGNESH SABARINATH

2. Introduction to MSDAP Aim: Performing basic audio signal processing computations using a programmable FIR filter. Implementation: Linear convolution described by the equation for FIR filter design.

3. Implementation To save computation time:  Multiplier is replaced by using the coefficients represented in Power of Two format (POT).  Use of 1 bit shift rather than employing a 16 bit shifter.

4. Rj = 0005 RJ values dictate the amount of coefficients to consider for calculating 1 u i value. The first u j will have 5 additions/subtractions given by the 5 coefficients. Coeff = 00B4 MSB corresponds to sign bit. 0 is addition and 1 is subtraction. Rest of the 8 bits represent the magnitude. The above coefficient is equivalent to adding the term x(n-180). After every u i is calculated we shift it and add it with the next ‘u i ’ in accordance with the equation shown above to generate the output for all 16 u i ’s. 010110100 00000101 Sample Computation

5. A system level abstraction of the MSDAP chip: A/D & D/A converter to sample inputs and make it available digitally. A controller unit that drives the processing unit (MSDAP) chip. System Setting

6. Signal Format - Input

7. Signal Format - Output

8. Reset 800 zeros in both channels Frame ‘0’ InReady ‘0’ Operation Modes Frame ‘0’ One non zero Reset Start

9. INITIAL STATE 0:

10. Entering State1 after initialization

11. Entering State2 on Frame ‘0’ to capture RJs

12. Entering State3 to wait for coefficients

13. Entering State4 on Frame ‘0’ to capture coefficients

14. Entering State5 to wait for data inputs

15. Entering State6 on Frame ‘0’ to begin computation

16. Entering State8 sleep state after 800 zeros in both channels

17. Entering back to State6 computation on receiving one non zero

18. Entering to State7 on Reset ‘0’ and back to State5 after reset

19. Challenges Flags– Synchronization issue. C Program output – Debugging internal working steps. Blocking/Non-blocking – scheduling assignments. Non overlapping variables – Multiple Driver issue.

20. C program computation snapshot

23. MSDAP I/O Pins Pin Name Type Pin No. Function VDDCPower3, 14 Connected to a well-decoupled +1.65V DC core power supply. VDDIOPower7, 19 Connected to a well-decoupled +1.65V DC I/O power supply VSS Grou nd 4, 8, 13, 18 The core and I/O ground pins connected to GND SCLKInput1  System Clock : 50 % duty cycle clock at the frequency 26.88 MHz.  Timing reference to the internal I/O control signals.  The InReady and OutReady signals are updated during the rising edge of Sclk.

24. Pin NameTypePin No.Function STARTInput15  When set HIGH the processor goes into initialization process.  Asynchronous with both Sclk and Dclk. Input 5Chip goes into Reset state on LOW for one DCLK. INREADY Output 12 It is set HIGH when the chip is ready to read the data from the controller. OUTREADYOutput11 It is set HIGH when the chip is ready to transmit the processed data to the controller. DCLKInput2  Data Clock: 50 % duty cycle at the frequency of 768 KHz.  Provides the timing reference for input sample transmission.  Inputs InputL/R are read during the falling edge. MSDAP I/O Pins

25. Pin NameTypePin No.Function INPUTL/INPUTRInput17 To carry the input samples serially to respective channels and is read at falling edge of DClk. OUTPUTL/OUTP UTR Output9 To carry the output processed samples of respective channels and transmitted at falling edge of SClk. FRAMEInput20 It aligns the serial coefficients, input and output samples. Set for one DClk when the controller transmits the sequence. NC 6Not connected MSDAP I/O Pins