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Lecture 7: Sequential Networks CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering.

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Presentation on theme: "Lecture 7: Sequential Networks CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering."— Presentation transcript:

1 Lecture 7: Sequential Networks CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

2 What is a sequential circuit? 2 “A circuit whose output depends on current inputs and past outputs” “A circuit with memory”

3 Part II. Sequential Networks (Ch. 3) Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables Main Theme: Timing Present time = t and next time = t+1 Timing constraints to separate the present and next times. Memory / Time steps Clock xixi yiyi sisi y i = f i (S t,X) s i t+1 = g i (S t,X) 3

4 Sequential Networks Memory Components –Hierarchy of Memory –Basic Mechanism of Memory –Types of Flip-Flops Implementation –Finite State Machine 4

5 The usage of a sequential machine 5 iClicker Question: A.Digital systems are implemented using sequential machines. B.Only a small subset of digital systems can be implemented using sequential machines. C.Sequential machines are too simple for complicated digital systems.

6 Hierarchy of Memory Devices Memory Bank (Farms of memory cells) Register (A vector of memory cells) Flip-Flop (One bit memory cell) –SR, D, T, JK flip-flops (Different types of memory cells) –State Tables (Truth table of sequential machine) –Characteristic Expressions (Switching algebraic expression of sequential machine) 6

7 Fundamental Memory Mechanism 7

8 Memory Mechanism: Capacitive Load Fundamental building block of sequential circuits Two outputs: Q, Q There is a feedback loop! In a typical combinational logic, there is no feedback loop. No inputs 8

9 Capacitive Loads Consider the two possible cases: –Q = 0: then Q’ = 1 and Q = 0 (consistent) –Q = 1: then Q’ = 0 and Q = 1 (consistent) –Bistable circuit stores 1 bit of state in the state variable, Q (or Q’ ) But there are no inputs to control the state 9

10 iClicker 10 Q. Given a memory component made out of a loop of inverters, the number of inverters has to be A.Even B.Odd

11 SR (Set/Reset) Latch SR Latch Consider the four possible cases: –S = 1, R = 0 –S = 0, R = 1 –S = 0, R = 0 –S = 1, R = 1 11

12 SR Latch Analysis –S = 1, R = 0: –S = 0, R = 1: 12

13 SR Latch Analysis –S = 1, R = 0: then Q = 1 and Q = 0 –S = 0, R = 1: then Q = 0 and Q = 1 13

14 SR Latch Analysis –S = 1, R = 1: 14

15 SR Latch Analysis –S = 0, R = 0: 15

16 SR Latch Analysis –S = 0, R = 0: then Q = Q prev –S = 1, R = 1: then Q = 0 and Q = 0 16

17 S R y Q Q = (R+y)’ y = (S+Q)’ 17

18 Flip-flop Components S R SR F-F (Set-Reset) Inputs: S, R State: (Q, y) y Q 18

19 Id Q(t) y(t) S R Q(t 1 ) y(t 1 ) Q(t 2 )y(t 2 ) Q(t 3 ) y(t 3 ) 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 1 2 0 0 1 0 1 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 0 1 0 1 0 1 5 0 1 0 1 0 1 0 1 0 1 6 0 1 1 0 0 0 1 0 1 0 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 1 0 1 0 1 0 9 1 0 0 1 0 0 0 1 0 1 10 1 0 1 0 1 0 1 0 1 0 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 0 1 0 1 14 1 1 1 0 0 0 1 0 1 0 15 1 1 1 1 0 0 0 0 0 0 Q y State Transition SR 10 00 11 00 10 SR 11 10 01 11 01 11 01 1000 10 00 01 00 11 State Diagram 01 19

20 CASES: SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing 20 Q. To avoid the SR latch output from toggling or behaving in an undefined way which input combinations should be avoided: A. (S, R) = (0, 0) B. (S, R) = (1, 1)

21 SR Latch Analysis –S = 0, R = 0: then Q = Q prev and Q = Q prev (memory!) –S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q) 21

22 CASES SR=01: (Q,y) = (0,1) SR=10: (Q,y) = (1,0) SR=11: (Q,y) = (0,0) SR = 00: if (Q,y) = (0,0) or (1,1), the output keeps changing Solutions: Avoid the two cases 1) SR = (0,0), 2) SR = (1,1). 0 0 0 1 - 1 1 0 1 - PS inputs 00 01 10 11 State table Q(t+1) SR Characteristic Expression Q(t+1) = S(t)+R’(t)Q(t) NS (next state) Q(t) 22

23 SR Latch Symbol SR stands for Set/Reset Latch –Stores one bit of state (Q) Control what value is being stored with S, R inputs –Set: Make the output 1 (S = 1, R = 0, Q = 1) –Reset: Make the output 0 (S = 0, R = 1, Q = 0) Must do something to avoid invalid state (when S = R = 1) 23

24 D Latch Two inputs: CLK, D –CLK: controls when the output changes –D (the data input): controls what the output changes to Function –When CLK = 1, D passes through to Q (the latch is transparent) –When CLK = 0, Q holds its previous value (the latch is opaque) Avoids invalid case when Q ≠ NOT Q 24

25 D Latch Internal Circuit 25

26 D Latch Internal Circuit 26

27 D Latch Internal Circuit 27

28 D Flip-Flop Two inputs: CLK, D Function –The flip-flop “samples” D on the rising edge of CLK When CLK rises from 0 to 1, D passes through to Q Otherwise, Q holds its previous value –Q changes only on the rising edge of CLK A flip-flop is called an edge-triggered device because it is activated on the clock edge 28

29 D Flip-Flop Internal Circuit 29

30 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When CLK = 0 –L1 is transparent, L2 is opaque –D passes through to N1 When CLK = 1 –L2 is transparent, L1 is opaque –N1 passes through to Q Thus, on the edge of the clock (when CLK rises from 0 1) –D passes through to Q 30

31 D Flip-Flop vs. D Latch 31

32 D Flip-Flop vs. D Latch 32

33 Latch and Flip-flop (two latches) A latch can be considered as a door CLK = 0, door is shutCLK = 1, door is unlocked A flip-flop is a two door entrance CLK = 1CLK = 0CLK = 1 33

34 D Flip-Flop (Delay) D CLK Q Q’ Id D Q(t) Q(t+1) 0 0 1 0 2 1 0 1 3 1 1 1 Characteristic Expression: Q(t+1) = D(t) 0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1) 34

35 iClicker 35 Can D flip-flip serve as a memory component? A.Yes B.No

36 JK F-F J CLK Q Q’ 0 0 0 1 ? 1 1 0 1 ? PS JK 00 01 10 11 State table Q(t+1) K 36

37 JK F-F J CLK Q Q’ Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t) 0 0 0 1 1 1 1 0 1 0 PS JK 00 01 10 11 State table Q(t+1) K 37

38 T CLK Q Q’ Characteristic Expression Q(t+1) = Q’(t)T(t) + Q(t)T’(t) 0 0 1 1 1 0 PS T 0 1 State table Q(t+1) T Flip-Flop (Toggle) 38

39 Using a JK F-F to implement a D and T F-F JKJK Q Q’ x CLK 39 iClicker What is the function of the above circuit? A.D F-F B.T F-F C.None of the above

40 Using a JK F-F to implement a D and T F-F JKJK Q Q’ T CLK T flip flop 40

41 Reading 41 [Harris] Chapter 3: 3.3, 3.4.1, 3.4.2

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