2. Flip Flop Chapter 15 Subject: Digital System Year: 2009

3. 3 Overview Latch and Flip Flop Propagation Delay, Set-up time, Hold time in the application of flip flop Apply flip flop in basic operation

4. Flip Flop Flip-flops are synchronous bistable devices, also known as bistable multivibrators. In this case, the term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK), which is designated as a control input, C; that is, changes in the output occur in synchronization with the clock. Bina Nusantara University 4

5. Edge-triggered Flip-Flop logic Symbol Bina Nusantara University 5

6. The Edge-Triggered S-R Flip-Flop Bina Nusantara University 6

7. The Edge-Triggered S-R Flip-Flop Bina Nusantara University 7

8. The Edge-Triggered S-R Flip-Flop Bina Nusantara University 8

9. The Edge-Triggered D Flip-Flop Bina Nusantara University 9

10. The Edge-Triggered J-K Flip-Flop Bina Nusantara University 10

11. The Edge-Triggered J-K Flip-Flop Bina Nusantara University 11

12. FLIP-FLOP OPERATING CHARACTERISTICS A propagation delay time is the interval of time required after an input signal has been applied for the resulting output change to occur. Four categories of propagation delay times are important in the operation of a flip-flop: –Propagation delay t PLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output. Bina Nusantara University 12

13. FLIP-FLOP OPERATING CHARACTERISTICS –Propagation delay t PHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output. Bina Nusantara University 13

14. Set-up Time Bina Nusantara University 14 The set-up time is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or Sand R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

15. Hold Time The hold time is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Bina Nusantara University 15

16. Flip Flop Application Bina Nusantara University 16