1. CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 11: Testing of Logic Circuits
Chapter 11

2. Testing of Logic Circuits
Must test a circuit to check that it meets required functional and timing specification.
Manufacturing process can introduce flaws.
Testing applies a set of inputs, called tests, and compare with expected outputs.
Challenge is to derive a small set of tests.
Exhaustive approach is impractical.

3. Faults Many things can go wrong:
Transistor may be stuck open or closed.
Wire can be shorted to Vdd or Gnd.
Wire may simply be broken.
Two wires may get shorted together.
Logic gate may produce the wrong output.

4. Stuck-At Model
Stuck-at model assumes a fault manifests as some wire stuck at a logic value of 0 or 1.
If w is stuck-at-0, it is denoted w/0.
If w is stuck-at-1, it is denoted w/1.
While this model does not work for all types of faults, works reasonably well.

5. Single and Multiple Faults
Dealing with multiple faults is difficult.
Considering single faults only still detects majority of multiple faults.
Fault detected when output value of faulty circuit differs from good circuit for a test.
Complete set of test is called a test set.

6. CMOS Circuits Transistors may be permanently open or shorted (closed).
May or may not appear as a stuck-at fault.
May also cause permanent path between Vdd and Gnd giving intermediate voltage.
May also lead to combinational circuit to behave like a sequential one.
Will restrict ourselves to stuck-at model.

7. Complexity of a Test Set
Sequential circuits substantially more complex to test than combinational ones.
In combinational case, we can apply all possible input valuations and check outputs.
This approach is impractical and unnecessary for large circuits.

8. Figure 11.1 Fault detection in a simple circuitw 1 f b w 2 w 3 d c
(a)
Circuit
Fault
detected
Test w w w 1 2 3
a/0
a/1
b/0
b/1
c/0
c/1
d/0
d/1 f /0 f /1
000   
001    
010    
011    
100  
101  
110  
111 
(b)
Faults
detected by
the
various
input
valuations
Figure Fault detection in a simple circuit

9. Figure 11.2 A sensitized pathw b 1 w = 1 2 c w = 3 f w = 1 4
Figure A sensitized path

10. Figure 11.3 Circuit for Example 11.1w c 1 w 2 b d f w 3 w 4
Figure Circuit for Example 11.1

11. Figure 11.4 Detection of faultsh k
fault
fault 1 b g
Figure Detection of faults
(a) Circuit g
(b) Detection of
(c) Detection of b c 1 2 3 4 1 2 3 4 1 2 3 4 w w w w w w w w w w w w

12. Figure 11.5 Circuit with a tree structure3 w 4 w 2 w f 3 w 4 w 1 w 2 w 3
Figure Circuit with a tree structure

13. Figure 11.6 Derivation of tests for the circuit in Figure 11.5
Product term
Test
No. w w w w w w w w w w w w w 1 3 4 2 3 4 1 2 3 1 2 3 4 1 1 1 1 1 1
Stuck-at-0 2 1 1 1 1 1 1 1 1
tests 3 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1
Stuck-at-1 6 1 1 1 1 1 1
tests 7 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1
Figure Derivation of tests for the circuit in Figure 11.5

14. Figure 11.7 All two-variable functions2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1
Figure All two-variable functions

15. h b w d 1 f w 2 c k
Figure The XOR circuit

16. Figure 11.9 The effect of various faults
Circuit
implements
b/0 f = w 5 2
b/1 f = w 10 2
c/0 f = w 3 1
c/1 f = w 12 1
d/0 f =
d/1 f = w + w 7 1 2
h/0 f = 1 15
h/1 f = w w 4 1 2
k/0 f = 1 15
k/1 f = w w 2 1 2
Figure The effect of various faults

17. Figure 11.10 Effectiveness of random testing
Percent
faults
detected
Number of tests
Figure Effectiveness of random testing

18. Testing Sequential Circuits
Response of sequential circuit is dependent on both current input and present state.
Could check all state transitions.
Cannot determine state, not observable.
Circuits must be designed to be testable.

19. Figure 11.11 Scan-path arrangement1
Combinational
circuit z k w n y 3 2 Y
Clock
Scan-in
Normal
Scan
Scan-out D Q

20. Figure 11.12 Circuit for Example 11.31 w y 2 z Y
Resetn
Scan-out
Normal/Scan
Scan-in
Clock D Q

21. Figure 11.13 The testing arrangementx p
Test
Circuit
Test
vector
under
result
generator
test
compressor x p n – 1 m – 1
Signature
Figure The testing arrangement

22. Figure 11.14 Pseudorandom binary sequence generator (PSRG)
Clock x x x x 3 2 1
PRBS
(a)
Circuit x 1 1 1 1 1 1 1 1 1
··· 3 x 1 1 1 1 1 1 1 1
··· 2 x 1 1 1 1 1 1 1 1
··· 1 x 1 1 1 1 1 1 1 1
··· f 1 1 1 1 1 1 1 1 1
···
(b)
Generated sequence
Figure Pseudorandom binary sequence generator (PSRG)

23. Figure 11.15 Single-input compressor circuit
Signature D Q D Q D Q D Q p Q Q Q Q
Clock
Figure Single-input compressor circuit

24. Figure 11.16 Multiple-input compressor circuit (MIC)
Signature D Q D Q D Q D Q Q Q Q Q
Clock p p p p 3 2 1
Figure Multiple-input compressor circuit (MIC)

25. Figure 11.17 BIST in a sequential circuit
Z-signature
Normal
Test
MIC Z W
Combinational X 1
circuit y Y
PRBSG-X
Scan-out
SIC
Y-signature
Flip-flops
and
multiplexers
Scan-in
PRBSG-y
Figure BIST in a sequential circuit

26. Figure 11.18 A four-bit built-in logic block observer (BILBO)D Q 1 M 2 S i n G
Clock p 3 q o u t
Figure A four-bit built-in logic block observer (BILBO)

27. Figure 11.19 Using BILBO circuits for testing
Scan-out
Combinational
Combinational
BILBO1
network
BILBO2
network
CN1
CN2
Scan-in
Figure Using BILBO circuits for testing

28. Boundary Scan
Chips soldered into printed circuit boards do not allow easy access it inputs/outputs.
Pins can be configured into a shift register to allow inputs and outputs to be scanned in.
Now IEEE Standard

29. Printed Circuit Boards
Need CAD software to design them.
Crosstalk – capacitively coupled wires.
Avoid long parallel wires.
Power supply noise – power supply spikes.
Use bypass capacitors between Vdd and Gnd.
Transmission-line effects
Use termination component on the line.

30. Testing of PCBs
Power Up – check for hot chips and correct power and ground voltages.
Reset – put circuit into known start state.
Low-level functional testing – use divide-and-conquer approach.

31. Testing of PCBs Full functional testing – test system.
Manufacturing errors.
Incorrect specifications.
Misinterpretation of the data sheets.
Wrong data sheets.
Timing – start with slow clock and gradually increase to desired frequency.
Reliability – affected by timing, noise, crosstalk issues, and environment.

32. Instrumentation
Oscilloscope – displays voltage waveforms to show problems with delay and noise.
Logic analyzer – allows examination of large groups of signals.

33. Where to go from here . . . CS/EE 3710 – Computer Design Laboratory
CS/EE 3720 – Analog and Digital Interfacing
CS/EE 3810 – Computer Architecture
CS/EE 4710 – Senior Project
CS/EE 5710 – Digital IC Design
CS/EE 5720 – Analog IC Design
CS/EE 5740 – CAD for Digital Circuits
CS/EE 5750 – Asynchronous Circuit Design
CS/EE 5810 – Advanced Computer Architecture
CS/EE 5830 – VLSI Architecture

34. New to the CE Program Tracks are no longer required.
Still must take 15 credits of CS/EE classes.
New senior thesis option:
Must take EE 3900 Junior seminar in Fall and prethesis in Spring (0.5 credits each).
Senior year must take one year of senior thesis for a total of 4 credits.
Do not need to take CS/EE 4710.
Can lead into a joint BS/EE degree.