1. Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii ISLPED’04

2. Outline Introduction Previous Work Algorithm Experimental Results Conclusion

3. Introduction Bellow.13 process leakage dominates power consumption – Leakage power = exp(-q*V t / K*T) Leakage reduction methods – Dual V t partition – MTCMOS – State assignment Low Vt logic module sleep Virtual ground high Vt

4. Outline Introduction Previous Work Algorithm Experimental Results Conclusion

5. sleep Previous Works MTCMOS – Take a non-negligible amount of time to wake up and re-activate sleep transistor. (long re- activation time) Virtual ground Low Vt logic module Vdd ONOFF VDD-Vth 0 Discharge Re-activation time Stand by mode Active mode

6. Previous Works Distributed sleep transistor – Multiple sleep transistors are initiated. – A faster re-activation time Most techniques presented at the logic and circuit level, and do not take placement information into account. Cause severe wiring congestion

7. Outline Introduction Previous Work Algorithm Experimental Results Conclusion

8. Sleep Transistor Insertion in row- based layout Low Vt logic module sleep Virtual ground high Vt Vdd local wiring

9. Row Compaction & Area Penalty Row Compaction Area Penalty Add sleep transistor

10. Gate Clustering Get Timing & floorplan Information from Layout Select a sleep transistor Check all rows? Yes No Row Compaction Select a cell Update maximum current available at sleep transistor Add cell to cluster Timing violation? No Yes sleep Virtual ground Gate 1 Gate 2 Gate n available current at sleep transistor According to available space A gate by gate exploration of each row

11. How to Select Cell? sleep Virtual ground Gate 1 Gate 2 Gate n ON Re-activation time If Arrival time > Re-activation time, zero re-activation delay overhead are paid. From primary output to primary input OFF Vdd Discharge Check whether the cell can be power-gated? 2.Current?3.Timing? RT>RT_OH? 1.Leakage Power?

12. Sleep Transistor Sizing sleep Virtual ground Gate 1 Gate 2 Gate N CL

13. Outline Introduction Previous Work Algorithm Experimental Results Conclusion

14. Experimental Results(1/2) Delay overhead constraint is set to 5% Area overhead constraint is set to 5% Benchma rk OrigOpt∆ PL [mW] Pdyn [mW] Ptot [mW] PL [mW] Pdyn [mW] Ptot [mW] PL [%] Pdyn [%] Ptot [%] Block10.110.290.40.020.320.3478.9-9.015.0 Block20.190.220.410.040.240.2880.0-10.131.0 Block30.160.310.470.040.330.3774.6-8.821.2 Block40.260.60.860.050.630.6882.7-5.018.6 Block50.120.290.410.030.320.3578.9-9.712.5 Block60.460.881.340.090.981.0783.5-12.420.1 Avg. 79.7-9.618.9

15. Experimental Results(2/2) Area Penalty BenchmarkGatesSleep Area_Ori g [µm2] Area_Opt [µm2] ∆[%] Block118521464912667942.9 Block219161465210667102.3 Block322152265053665502.3 Block422671365412665241.7 Block523022665918681593.4 Block626122070298717032.0

16. Experimental Results(3/3) Delay penalty Cell No Leak ControlLeak Control∆Power [%] ∆Delay [%] PLk[mW]Delay[ps]PLk[mW]Delay[ps] G17.761132.32.717137.065.0-3.5 G27.881132.22.371135.069.0-2.1 G311.278120.81.466126.187.0-4.3 G41.951161.30.547166.371.9-3.1 G51.988158.30.467165.376.5-4.4 G62.161161.00.737168.365.8-4.5 G74.967130.30.745135.185.0-3.6 G85.704185.01.254189.078.0-2.1 G91.136146.70.353152.568.9-3.9 G101.968240.00.446248.077.3-3.3 G114.967182.60.745188.285.1-3.0 G123.054369.60.916385.770.0-4.3

17. Outline Introduction Previous Work Algorithm Experimental Results Conclusion

18. Sleep Transistor Insertion : – Driven by a layout-aware cost function – Done with tunable performance and area penalty