1. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić November 2002.

2. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 2 Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

3. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 3 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

4. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 4 Static Complementary CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … …

5. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 5 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

6. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 6 PMOS Transistors in Series/Parallel Connection

7. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 7 Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D

8. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 8 Complementary CMOS Logic Style

9. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 9 Example Gate: NAND

10. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 10 Example Gate: NOR

11. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 11 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

12. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 12 Constructing a Complex Gate

13. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 13 Properties of Complementary CMOS Gates Snapshot High noise margins: V OH andV OL are atV DD andGND, respectively. No static power consumption: There never exists a direct path betweenV DD and V SS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions)

14. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 14 CMOS Properties  Full rail-to-rail swing; high noise margins  Logic levels not dependent upon the relative device sizes; ratioless  Always a path to Vdd or Gnd in steady state; low output impedance  Extremely high input resistance; nearly zero steady-state input current  No direct path steady state between power and ground; no static power dissipation  Propagation delay function of load capacitance and resistance of transistors

15. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 15 Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 INV NOR2

16. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 16 Input Pattern Effects on Delay  Delay is dependent on the pattern of inputs  Low to high transition  both inputs go low –delay is 0.69 R p /2 C L  one input goes low –delay is 0.69 R p C L  High to low transition  both inputs go high –delay is 0.69 2R n C L CLCL B RnRn A RpRp B RpRp A RnRn C int

17. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 17 Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0  1 67 A=1, B=0  1 64 A= 0  1, B=1 61 A=B=1  0 45 A=1, B=1  0 80 A= 1  0, B=1 81 NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF

18. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 18 Transistor Sizing CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL 2222 22 1 1 4444

19. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 19 Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C 1 2 22 4 4 8 8 6 3 6 6

20. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 20 Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

21. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 21 t p as a Function of Fan-In t pL H t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided. t pH L quadratic linear tptp

22. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 22 t p as a Function of Fan-Out t p NOR2 t p (psec) eff. fan-out All gates have the same drive current. t p NAND2 t p INV Slope is a function of “driving strength”

23. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 23 t p as a Function of Fan-In and Fan-Out  Fan-in: quadratic due to increasing resistance and capacitance  Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO

24. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 24 Fast Complex Gates: Design Technique 1  Transistor sizing  as long as fan-out capacitance dominates  Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks

25. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 25 Fast Complex Gates: Design Technique 2  Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 1 1 0101 charged discharged

26. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 26 Fast Complex Gates: Design Technique 3  Alternative logic structures F = ABCDEFGH

27. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 27 Fast Complex Gates: Design Technique 4  Isolating fan-in from fan-out using buffer insertion CLCL CLCL

28. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 28 Fast Complex Gates: Design Technique 5  Reducing the voltage swing  linear reduction in delay  also reduces power consumption  But the following gate is much slower!  Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.69 (3/4 (C L V swing )/ I DSATn )

29. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 29 Sizing Logic Paths for Speed  Frequently, input capacitance of a logic path is constrained  Logic also has to drive some capacitance  Example: ALU load in an Intel’s microprocessor is 0.5pF  How do we size the ALU datapath to achieve maximum speed?  We have already solved this for the inverter chain – can we generalize it for any type of logic?

30. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 30 Buffer Example For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N (in units of  inv )

31. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 31 Ratioed Logic

32. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 32 Ratioed Logic

33. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 33 Ratioed Logic

34. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 34 Active Loads

35. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 35 Pseudo-NMOS

36. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 36 Pseudo-NMOS VTC 0.00.51.01.52.02.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V in [V] V o u t W/L p = 4 W/L p = 2 W/L p = 1 W/L p = 0.25 W/L p = 0.5

37. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 37 Improved Loads (2) V DD V SS PDN1 Out V DD V SS PDN2 Out A A B B M1M2 Differential Cascode Voltage Switch Logic (DCVSL)

38. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 38 DCVSL Example

39. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 39 DCVSL Transient Response Time [ns] V o l t a g e [V] A B A,B A,B

40. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 40 Pass-Transistor Logic

41. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 41 Pass-Transistor Logic

42. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 42 Example: AND Gate

43. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 43 NMOS-Only Logic 00.511.52 0.0 1.0 2.0 3.0 Time [ns] V o l t a g e [V] x Out In

44. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 44 NMOS-only Switch A =2.5 V B C =2.5 V C L A =2.5 V C =2.5 V B M 2 M 1 M n Threshold voltage loss causes static power consumption V B does not pull up to 2.5V, but 2.5V - V TN NMOS has higher threshold than PMOS (body effect)

45. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 45 NMOS Only Logic: Level Restoring Transistor M 2 M 1 M n M r Out A B V DD V Level Restorer X Advantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem

46. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 46 Restorer Sizing W/L r =1.0/0.25 W/L r =1.25/0.25 W/L r =1.50/0.25 W/L r =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack

47. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 47 Solution 2: Single Transistor Pass Gate with V T =0 Out V DD V 2.5V V DD 0V 2.5V 0V WATCH OUT FOR LEAKAGE CURRENTS

48. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 48 Complementary Pass Transistor Logic

49. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 49 Solution 3: Transmission Gate A B C C A B C C B C L C = 0 V A =2.5 V C =2.5 V

50. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 50 Resistance of Transmission Gate

51. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 51 Pass-Transistor Based Multiplexer GND V DD In 1 In 2 SS S S

52. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 52 Transmission Gate XOR A B F B A B B M1 M2 M3/M4

53. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 53 Delay in Transmission Gate Networks C R eq R CC R C In m (c)

54. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 54 Delay Optimization

55. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 55 Transmission Gate Full Adder Similar delays for sum and carry

56. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 56 Dynamic Logic

57. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 57 Dynamic CMOS  In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path.  fan-in of n requires 2n (n N-type + n P-type) devices  Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.  requires on n + 2 (n+1 N-type + 1 P-type) transistors

58. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 58 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

59. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 59 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)

60. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 60 Conditions on Output  Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.  Inputs to the gate can make at most one transition during evaluation.  Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

61. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 61 Properties of Dynamic Gates  Logic function is implemented by the PDN only  number of transistors is N + 2 (versus 2N for static complementary CMOS)  Full swing outputs (V OL = GND and V OH = V DD )  Non-ratioed - sizing of the devices does not affect the logic levels  Faster switching speeds  reduced load capacitance due to lower input capacitance (C in )  reduced load capacitance due to smaller output loading (Cout)  no I sc, so all the current provided by PDN goes into discharging C L

62. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 62 Properties of Dynamic Gates  Overall power dissipation usually higher than static CMOS  no static current path ever exists between V DD and GND (including P sc )  no glitching  higher transition probabilities  extra load on Clk  PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn  low noise margin (NM L )  Needs a precharge/evaluate clock

63. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 63 Issues in Dynamic Design 1: Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is subthreshold current

64. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 64 Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

65. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 65 Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

66. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 66 Charge Sharing Example C L =50fF Clk AA B B B!B CC Out C a =15fFC c =15fFC b =15fFC d =10fF

67. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 67 Charge Sharing B  0 Clk X C L C a C b A Out M p M a V DD M b Clk M e

68. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 68 Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

69. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 69 Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0

70. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 70 Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2

71. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 71 Issues in Dynamic Design 4: Clock Feedthrough CLCL Clk B A Out MpMp MeMe Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

72. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 72 Clock Feedthrough Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feedthrough

73. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 73 Other Effects  Capacitive coupling  Substrate coupling  Minority charge injection  Supply noise (ground bounce)

74. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 74 Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 VV V Tn Only 0  1 transitions allowed at inputs!

75. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 75 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1  1 1  0 0  0 0  1

76. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 76 Why Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

77. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 77 Properties of Domino Logic  Only non-inverting logic can be implemented  Very high speed  static inverter can be skewed, only L-H transition  Input capacitance reduced – smaller logical effort

78. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 78 np-CMOS In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

79. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 79 NORA Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 to other PDN’s to other PUN’s WARNING: Very sensitive to noise!