1. 11-1 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Latch-up & Power Consumption Latch-up Problem Latch-up condition  1   2 >1 GND Vdd R sub RwRw 11 22 I 1  I2 I2  VWVW

2. 11-2 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon I VLVL V dd -GND (I/o drive /pads)

3. 11-3 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Latch-up Solutions 1) Reduce  R W, R sub 2) Many contacts to substrate and well 3) Guard rings for transistors with W > 100  m GND BrownGreen V dd 4) E pi -layer 5) SOI NMOS PMOS P+P+ N+N+

4. 11-4 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon CMOS Latch-up and It’s Preventions  What is CMOS Latch-up? — CMOS latch-up is a parasitic circuit effect in which both npn and pnp transistors are turned on at the same time. The result of this effect is the shortening of the V DD and V SS lines. Current no longer flows thru the surface channel, but thru the bulk and the junctions, the signal outputs will be latched at an unknown state (  0.85~1.5V). — IDD current will increase until they self-limit or until they result in the destruction of the chip or it’s bonding leads. — Once it is being latched, the only way to restore it’s function is to turn off/on the power. For example: n-well CMOS epi technology

5. 11-5 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon  npn =0.5~10 depends on the distance between n + to n-well  pnp =50~100 depends on the base width (X JN-well —X JP+ ) R W =1k  ~20k  depends on N-well sheet resistance and distance between n + and P + R S =10  (for p - / p + epi) 500-700  for bulk substrate

6. 11-6 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon  How to prevent latch-up? — Reduce current gain of parasitic bipolar transistor   npn   pnp >1 by suitable vertical process design and horizontal spacings. But for high packing density VLSI, this is difficult to achieve. — Reduce Rs and Rw Rw, by putting more n-well plugs (V DD ) or sorrunding n-well with n + guard rings. Rs, by putting more p+ plugs (ground) in substrate, or with p - /p + epitaxial layer substrate. — Put top side ring as surface ground contact or use backside contact as ground. — Use trench isolation or silicon on Sapphare Sustrate. — If use epi, n+ —p+ spacing should be greater than the epitaxial thickness. — Special attention on the I / O pad, put guard rings around the buffer circuit.

7. 11-7 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon ESD (Electrostatic Discharge) concerns in Input Protection Circuit Human body model Typical input protection circuit 1.5k  2000V 1000pF Total energy stored 1/2CV 2 =0.2  10 -3 J Finger tip pad 1~2k  V DD Two mechanisms in ESD effect. 1. Oxide rupture 2. Poly Si resistor, or pn junction burned out.

8. 11-8 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Si SiO 2 SiO 2 dielectric strength 6  10 6 V/cm (thinner oxide, the dielectric strength even higher) if 650Å, BV=39V if 300Å, BV=25V The voltage that can build up on a gate may be determined from If charging current 10  A, charging time 1  s, C g =0.03pF, then V=330V !!! It will definitely rupture gate oxide. Conventionally, use two clamping diodes plus one resistor (1~2K  ), this resistor is for current limiting purpose, preferably using poly silicon line, but the strength of poly is not as good as that of a diffusion resistor. In high speed circuit, one should watch out the extra RC delay due to current limiting resistor. The area of clamping diodes will determine power dissipation capability.

9. 11-9 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Some Layout Precautions on latch-up 1. Separate PMOS. NMOS driver transistors 2. P + guard rings around NMOS and connected to V SS 3. N + guard rings around PMOS and connected to V DD PMOS N+N+ V DD NMOS P+P+ V SS PAD 4. Employ minimum area P-well, minimize photo current during transistor. 5. Source fingers of PMOS / NMOS prefer to be perpendicular to the current flow direction   Current direction PMOS NMOS

10. 11-10 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 6. P-well should hard wired to GND, N-sub should hard wired to V DD, V DD, V SS face each other. n+n+ n+n+ n+n+ n+n+ P+P+ P+P+ P+P+ P+P+ tied to V DD by metal from V DD line, not just got V DD from substrate. P-well tied to GND by metal running over 7. Spacing between p + and n + (in p-well) should be minimum (“d” can be zero.) Spacing between n-sub n + and p + source should be minimum. p+p+ p+p+ p+p+ n+n+ n+n+ n+n+ d d P-P- n-n-

11. 11-11 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Potential Well/Sub Contact Problem p+p+ p+p+ n+n+ n+n+ SD p-sub Signal GND Misplaced Substrate Contact Signal (Drain) p + /p-sub n + (source)

12. 11-12 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon p+p+ p+p+ SD in out n-well CLK Floating Well Pass Transistor (DON’T FORGET WELL TABS!) V dd CLK out in IN V G V well V out 0 1(off) u 0 1 0(on) V X 1 (V DD - V D,on ) 1(off) V X 1 0 0(on) V X 0 0 1(off) V X 0 0  1 1(off) V X 1

13. 11-13 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Power Consumption For CMOS (1) Static dissipation If there is no pseudo NMOS pull-rp or other resistive current path, the only static power dissipation is from junction leakage. A useful estimate is to allow a leakage current of 0.1nA to 0.5nA per gate at room temperature.  Junction Leakage 10 6 gate circuits I total = 0.5nA  10 6 =0.5mA Power = I total  5V=2.5mW  Gate Leakage (10pA/  m)  (10  m)  10M ~1mA Power = 1mA  5V= 5mW

14. 11-14 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Power Consumption in CMOS (cont’d) (2) Dynamic Power R R

15. 11-15 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Dynamic dissipation (cont’d) (a) Switching transient current P sw (small) V DD V DD - | V tp | V tn t1t1 t2t2 t3t3  Slow rising/falling results in power dissipation of noise susceptibility (P sw  as tr  ) I sw t t

16. 11-16 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Dynamic dissipation (cont’d) (b) Charging and discharging of load capacitance (dominant) If the chip function consists of several frequencies, then the total power consumption will be: Note: the power dissipation is independent of the device parameters Ex :

17. 11-17 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Power consumption For NMOS For NMOS inverter, assume 50% duty cycle For minimum power W L =W min, L L =k R L min