1. Sequential Logic Circuits

2. Combinational logic circuit
A combinational logic circuit is one whose outputs depend only on its current inputs. 1 2 3 4

3. Sequential Logic Circuits
A Sequential Logic Circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. 2

4. Sequential Logic Circuits
The circuit controlled by the channel-up and channel-down pushbuttons on a TV is a sequential circuit.
The channel selection depends on the past sequence of up/down pushes and the current push. 2

5. The current “state”
It is inconvenient, and often impossible, to describe the behaviour of a sequential circuit by means of a table that lists outputs as a function of the input sequence that has been received up until the current time.
To know where you are going next, you need to know where you are now.
With the TV channel selector, it is impossible to determine what channel is currently selected by looking only at the preceding sequence of presses, whether we look at the preceding 10 presses or the preceding 1000.
More information, the current “state” of the channel selector, is needed.

6. “state”
The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behaviour.
In the channel-selector example, the current channel number is the current state.
Inside the TV, this state might be stored as seven binary state variables representing a decimal number between 1 and 9.
Given the current state (channel number), we can always predict the next state as a function of the inputs (up/down pushes).

7. “finite-state machines”
In a digital circuit, state variables have binary values.
A circuit with n binary state variables has 2n possible states.
As large it might be, 2n is always finite, so sequential circuits are sometimes called finite-state machines.

8. combinational circuit
A logic circuit whose outputs depend only on its current inputs is called a combinational circuit.

9. combinational circuit
Logic circuit using AND, OR and NOT gates:

10. Sequential Logic Circuits
outputs depend on the sequence of past inputs.
As a result, the circuit must “remember” something about the past.

11. Sequential Logic Circuit
A circuit with memory, whose outputs depend on the current input and the sequence of past inputs, is called a sequential circuit.
The behaviour of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input.

12. Sequential Logic Circuit
A Sequential Logic circuit consists of a combinational circuit to which memory elements are connected to form a feedback path.
The memory elements are devices capable of storing binary information within them.
The binary information stored in the memory elements at any given time defines the state of the sequential circuit.
The sequential circuit receives binary information from external inputs.
These inputs, together with the present state of the memory elements, determine the binary value at the output terminals.

13. Sequential Logic Circuit
The block diagram demonstrates that the external outputs in a sequential circuit are a function not only of external inputs, but also of the present state of the memory elements.
The next state of the memory elements is also a function of external inputs and the present state.
Thus a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.

14. Memory elements
The memory elements commonly used in sequential circuits are time-delay devices.
The memory capability of a time-delay device is due to the finite time it takes for the signal to propagate through the device.
In practice, the internal propagation delay of logic gates is of sufficient duration to produce the needed delay, so that physical time-delay units may be unnecessary.
In gate-type sequential circuits, the memory elements consist of logic gates whose propagation delays constitute the required memory.
Thus a sequential circuit may be regarded as a combinational circuit with feedback only.

15. Memory elements
The output of this NOT gate holds the previous value for a length of time equals the propagation delay of this gate.
For input 0 the output is 1.
Now if we change the input to 1 the corresponding output will be 0 but after a certain amount of time (equal to the propagation delay).
That is the gate is holding the previous value for a certain time and thus working as a memory.

16. Memory elements
That is the gate is holding the previous value for a certain time and thus working as a memory.

17. Memory elements
That is the gate is holding the previous value for a certain time and thus working as a memory.

18. Setup and Hold Times These times are related to the clock input.
Input should not be changed during these times.

19. Memory elements
The delay can be increased by cascading the gates.

20. Bistable element The simplest sequential circuit
Two states - bistable circuit
One state variable, say, Q
HIGH
LOW
LOW
HIGH

21. Bistable element The simplest sequential circuit Two states
One state variable, say, Q
LOW
HIGH
HIGH
LOW

22. How to control a Bistable element?
Screwdriver
Control inputs
The danger of connecting the control input to ground: You are basically connecting the output to the ground that has low internal resistance, i.e. short circuiting.
+5 v
LOW
HIGH
HIGH
LOW

23. Solution….
R (Reset) Q Q
S (Set)

24. SR Latch

25. A bistable with control inputs
How to control it?
Screwdriver
Control inputs
S-R latch

26. Analyse the operation of the FF_NOR circuit
The output of a NOR gate is 0 if any input is 1, and
the output is 1 when all inputs are 0.
1. As a starting point, assume that the S input is 1 and the R input is 0.
Since the lower gate has an input of 1, its output Q must be 0, which puts both inputs of upper gate at 0, so that output Q is 1.
2. When the S input is returned to 0, the outputs remain the same, because Q remains at 1 that is one input of Q at 1 that causes Q to stay at 0. So, both inputs are at 0 results Q at 1.

27. Analyse the operation of the FF_NOR circuit
In the same manner, it is possible to show that a 1 in the R input changes Q to 1 and Q’ to 0.
1. As a starting point, assume that the S input is 0 and the R input is 1.
Since the upper gate has an input of 1, its output Q must be 0, which puts both inputs of lower gate at 0, so that output Q is 1.
3. When the R input is returned to 0, the outputs remain the same, because Q remains at 1 that is one input of Q at 1 that causes Q to stay at 0. So, both inputs are at 0 results Q at 1.

28. Analyse the operation of the FF-NAND circuit
The output of a NAND gate is 1 if any input is 0, and
the output is 0 when all inputs are 1.
1. As a starting point, assume that the S input is 0 and the R input is 1.
Since the upper gate has an input of 0, its output Q must be 1, which puts both inputs of lower gate at 1, so that output Q is 0.
2. When the S input is returned to 1, the outputs remain the same, because Q remains at 1 that is one input of Q at 0 that causes Q to stay at 1. So, both inputs are at 1 results Q at 0.
S_L
R_L 1
S_L 1
R_L 1

29. Analyse the operation of the FF- NAND circuit
In the same manner, it is possible to show that a 0 in the R input changes Q to 1 and Q to 0.
1. As a starting point, assume that the S input is 1 and the R input is 0.
Since the lower gate has an input of 0, its output Q must be 1, which puts both inputs of upper gate at 0, so that output Q is 1.
3. When the R input is returned to 1, the outputs remain the same, because Q remains at 0 that is one input of Q at 0 that causes Q to stay at 1. So, both inputs are at 1 results Q at 0.
S_L
R_L 1
S_L 1 1
R_L

30. Types of sequential circuits
There are two main types of sequential circuits:
synchronous
asynchronous
their classification depends on the timing of their signals.
A synchronous sequential circuit is a system whose behaviour can be defined from the knowledge of its signals at discrete instants of time.
The behaviour of an asynchronous sequential circuit depends upon the order in which its input signals change and can be affected at any instant of time.

31. Asynchronous Sequential Logic Circuit
An asynchronous sequential circuit uses ordinary gates and feedback loops. Propagation delay of these gates provide the needed memory, thereby creating sequential-circuit building blocks such as latches and flip-flops that are used in higher- level designs.

32. SR Latch behaviour

33. SR Latch with NOR gates

34. SR Latch with NAND gates
S_L
R_L 1
S_L 1 1
R_L

35. SR Flip-flop with Control Input

36. SR Flip_Flop with Clock input

37. SR Flip_Flop with Clock input
Q is an abbreviation of Q(t), referred to as the present state.
Q(t+1), referred to as the next state after application of a single pulse at the clock input.

38. Boolean equation for SR Flip-Flop

39. D Flip-Flop; ensures S & R are never equals 1 at the same time

40. D Flip-Flop with Clock input
Q(t+1) = Q.D + Q.D = D.(Q +Q) = D.1 = D

41. Boolean equation for D Flip-Flop

42. Synchronous Sequential Logic Circuit
A synchronous sequential circuit , by definition, must employ signals that affect the memory elements only at discrete instants of time.
One way of achieving this goal is to use pulses of limited duration throughout the system.
the device that generates these pulses are called clock and the train of pulses are called clock pulses.

43. Synchronous Sequential Logic Circuit
A synchronous sequential circuit , by definition, must employ signals that affect the memory elements only at discrete instants of time.
Storage
elements

44. SR Flip_Flop with Clock input

45. Clock
The state changes of most sequential circuits occur at times specified by a free-running clock signal.
Active high clock signal:

46. Clock
Active low clock signal:

47. Clock period, frequency
The clock period is the time between successive transitions in the same direction.
The clock frequency is the reciprocal of the period. i.e., the number of clock pulses per second.
f = 1/t

48. Duty cycle
Duty cycle is the percentage of time that the clock signal is at its asserted level.

49. Pentium 4
What is the clock frequency of the latest Pentium 4 processor?
What is the clock period of the latest Pentium 4 processor?

50. sequential circuit
A circuit with memory, whose outputs depend on the current input and the sequence of past inputs, is called a sequential circuit.

51. Sequential Logic Circuit
A Sequential Logic circuit consists of a combinational circuit to which memory elements are connected to form a feedback path.
The memory elements are devices capable of storing binary information within them.
The binary information stored in the memory elements at any given time defines the state of the sequential circuit.
The sequential circuit receives binary information from external inputs.
These inputs, together with the present state of the memory elements, determine the binary value at the output terminals.

52. Bistable element The simplest sequential circuit
Two states - bistable circuit
One state variable, say, Q
HIGH
LOW
LOW
HIGH

53. Bistable element The simplest sequential circuit Two states
One state variable, say, Q
LOW
HIGH
HIGH
LOW

54. Analog analysis Assume pure CMOS thresholds, 5V rail
Theoretical threshold center is 2.5 V

55. Analog analysis Assume pure CMOS thresholds, 5V rail
Theoretical threshold center is 2.5 V
2.5 V
2.5 V
2.5 V
2.5 V

56. Analog analysis Assume pure CMOS thresholds, 5V rail
Theoretical threshold center is 2.5 V
2.5 V
4.8 V
2.51 V
2.0 V
0.0 V
2.5 V
2.5 V
0.0 V
5.0 V
4.8 V
2.5 V

57. Metastability Metastability is inherent in any bistable circuit
Two stable points, one metastable point

58. Another look at metastability

59. “sube y baja” behavior

60. Why all the harping on metastability?
All real systems are subject to it
Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times.
Details in Chapter-7 flip-flop descriptions and in Section 8.9 (later in quarter).
Especially severe in high-speed systems
since clock periods are so short, “metastability resolution time” can be longer than one clock period.
Many digital designers, products, and companies have been burned by this phenomenom.

61. S-R latch operation
Metastability is possible if S and R are negated simultaneously.
(try it in Foundation)

62. S-R latch timing parameters
Propagation delay
Minimum pulse width

63. S-R latch symbols

64. D latch

65. D flip-flop timing parameters
Although the D filp-flop eliminates the S=R=1 problem of the SR Flip-flop, it does not eliminate the metastability problem.

66. D flip-flop advantages
This device has two advantages over the clocked RS flip-flop:
(i) The indeterminate state is eliminated, and
(ii) There is a single input that can be used for Setting or Resetting.
It is really a clocked RS flip-flop.
This device “remembers” the value of the input “D” (Data in) when CP was last “high.”
When CP=0, D is ignored.
When CP=1, D is accepted and effectively passed through to Q transparently.
Often this device is called a “Transparent Latch.”

67. D- flip-flop timing parameters
Propagation delay (from C or D)
Setup time (D before C edge)
Hold time (D after C edge)

68. D flip-flop timing parameters
Propagation delay (from CLK)
Setup time (D before CLK)
Hold time (D after CLK)

69. Edge-triggered D flip-flop behavior

70. Other D flip-flop variations
Negative-edge triggered
Clock enable
Scan

71. Scan flip-flops -- for testing
TE = 0 ==> normal operation
TE = 1 ==> test operation
All of the flip-flops are hooked together in a daisy chain from external test input TI.
Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.

72. J-K flip-flops
The most sophisticated flip flop is the “J-K Flip-Flop.”
It has two inputs J and K which can be in any one of four states, 00, 01, 10, and 11. Each of these states will have a unique effect on the device.
On the next CP, the device will do one of four things depending on the states of the J and K inputs.
It may:
1/ Complement its current state
2/ Make no change to its current state
3/ Become “Set” (or stay set if it already is set)
4/ Become “Reset” (or stay reset if it already is reset)

73. J-K flip-flops
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type.
J is equivalent to S and K is equivalent to R.
when both inputs J and K are equal to 1, the flip-flop switches to its complement state.

74. J-K flip-flops

75. J-K flip-flops

76. J-K flip-flops

77. T flip-flops

78. T flip-flops

79. level triggered
All the flip flops studied so far were “level triggered” devices.
The particular devices we looked at were all “Hi-level triggered flip flops.”
This means that they respond to input conditions whenever CP is a logic 1.
By inverting the clock signal with the addition of an inverter, we could have made these devices “Low-level triggered.”

80. edge triggered
Often, it is desirable to have flip-flops respond to their input conditions only when there is a transition in the state of the clock input. i.e. we want the device to ignore inputs when the clock is high and when it is low too!
We want it to respond only when the clock changes.
If the device responds when the clock changes from a logic 1 to a logic 0, we say that the device is a “negative (going) edge triggered device.”
If it responds when the clock changes from a logic 0 to a logic 1, we say that the device is a “positive (going) edge triggered device.”
We will look at a timing diagram to further explain the concept of an edge.

81. master-slave” arrangement
One way to achieve “edge-triggering” is to combine a “high level triggered” device with a “low level triggered” device in a “master-slave” arrangement.
If the master responds to inputs only when CP is high, and the slave only when CP is low, then we have a device that responds to inputs only during a “negative going edge.”
Likewise, if the master responds to inputs only when CP is low, and the slave only when CP is high, then we have a device that responds to inputs only during a “positive going edge.”
We will look at an example of a “Master-Slave D-Type Flip-Flop” and a sample timing diagram of its behaviour.

82. Master-Slave flip-flop

83. Timing of Master-Slave flip-flop

84. Dynamic Indicator
Finally, edge triggered devices have their clock inputs shown with a “Dynamic Indicator” to indicate that they respond to a transition.
Both positive and negative dynamic indicators will be given in two diagrams.

85. J-K flip-flops

86. T flip-flops
Important for counters

87. Flip-Flop Characteristic Tables

88. Standard Graphic Symbols for Latch and Flip-Flops

89. Standard Graphic Symbols for Latch and Flip-Flops