1. 2. Sissejuhatus teooriasse
Teooria: Boole’i differentsiaalvõrrand
Teooria: Binaarsed otsustusdiagrammid
Rike
Test
Testi süntees
Diagnostika sõnastik
Testi analüüs – rikete simuleerimine
Stiimul
Digitaal- süsteem
Reaktsioon
Diagnoos 4 1 2 3

2. Fault Propagation Problem
Logic gate 1
Path
activation
Fault
Stuck - at
Correct
signal
Error x 2 3 = 4 5 6 7 y F ( X )
Logic circuit
& 1
Path activation
Fault “
Stuck - at ”
activation
Correct
signal
Error

3. Boolean derivatives Y = F(x) = F(x1, x2, … , xn) Boolean function:
Boolean partial derivative:

4. Boolean Derivatives Useful properties of Boolean derivatives:
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at xi
If F(x) is independent of xi
Näide:

5. Boolean derivatives Examples: - if F(x) is independent of xi
if F(x) depends always on xi
Examples:

6. Boolean vector derivatives
If multiple faults take place independent of xi
Example:

7. Boolean vector derivatives
Calculation of the vector derivatives by Carnaugh maps: x2 x2 x2 1 1 1 1 1 1  = 1 1 x3 x3 1 1 1 1 1 1 1 1 x3 x1 x1 x1 1 1 1 1 1 1 1 1 x4 x4 x4

8. Boolean vector derivatives
Interpretation of three solutions:
Two paths activated 1
Single path activated 1

9. Derivatives for complex functions
Boolean derivative for a complex function:
Example:
Additional condition:

10. Topological Idea of Test Generation1
Path
activation
Fault
Stuck - at
Correct
signal
Error x 2 3 = 4 5 6 7 y F ( X ) x 1 2 y 3 4 5 6 7 1 1

11. Mapping Between Circuit and SSBDD
Each node in SSBDD represents a signal path:
x11 y
x21
x12
x31 x4
x13
x22
x32 1
Signal path
Node x11 in SSBDD represents the path (x1, x11, x6, y ) in the circuit
The SAF-0(1) fault at the node x11 represents the SAF faults on the lines x11, x6, y in the circuit  fault collapsing
32 faults (16 lines) in the circuit  16 faults (8 nodes) in SSBDD

12. Test Generation with BD and BDDy x1 x2
BD: x3 x2 x4 x1 x4 x5 1 x2 x6
Test pattern: x1 x2 x1 x2 x3 x4 x5 x6 y 1 - D

13. Fault Analysis with SSBDDs
Algorithm:
Determine the activated path to find the fault candidates
Analyze the detectability of the each candidate fault (each node represents a subset of real faults)
& 1 x1 x2 x3 x4 y
x11
x21
x12
x31
x13
x22
x32
x11 y
x21
x12
x31 x4
x13
x22
x32 1

14. Test Generation with SSBDDs
& 1 x1 x2 x3 x4 y
Test generation for:
x11
x21
x12
x31
x13
x22
x32
x110
10
x11 y
x21
x12
x31 x4
x13
x22
x32 1
10
Structural BDD: x1 y x2 x4 x3
Functional BDD: 1
10
x1 x2 x3 x4 y
Test pattern:
1 0

15. Functional Synthesis of BDDs
Shannon’s Expansion Theorem: xk y
Using the Theorem
for BDD synthesis: 1 x1 x2 1 x3 x4 x3 x4 1

16. Functional Synthesis of BDDs
Shannon’s Expansion Theorem: x1 x2 1 x3 x4 x1 x3 x2 1 x4

17. BDDs for Logic Gates Elementary BDDs: SSBDD synthesis: OR AND NORx1 x2 x3 y
&
AND 1 1 x2 x3 y x1 OR 1 1 x1 x2 x3 y
NOR
Given circuit:
& 1 x1 x2 x3
x21
x22 y a b
SSBDD synthesis:
SSBDDs for a given circuit are built by superposition of BDDs for gates

18. Synthesis of SSBDD for a Circuit
Superposition of BDDs:
Given circuit: a b y x1 a
x21 1 x2 y
& b
x22 x3
x22 a y
x22 x3 b 1 x3 b
Structurally Synthesized BDD:
Compare to a x1
x21 x3 y
x22 x1
x21 a
Superposition of Boolean functions:

19. Logic Operation with BDDs
Generation of BDDs for

20. Boolean Operations with SSBDDs
AND-operation:
y = e  g x3 x1
x21
x22 x6 x4
x51
x52 y 1
& x1 x2 x3
x21
x22 y a b x5 x6
x51
x52 c d x4 g e
OR-operation: x3 x1
x21
x22 y x6 x4
x51
x52
y = e  g

21. Properties of SSBDDs Boolean function: y = x1x2  x3 (x4  x5x6)#1 #0 x3 x4 x5 x6 y
0-nodes of a 0-path represent
a term in the CNF: x1x4x5 = 0 x2 #1 x3 x6 #0 x1 x4 x5
1-nodes of a 1-path represent
a term in the DNF: x3x5x6 = 1

22. Boolean Operations with SSBDDs
Boolean function:
Inverted function (DeMorgan):
y = x1x2  x3 = ( x1  x2) x3 y x1 x3 x2
y = x1x2  x3 y x1 x2 x3
Dual function: y*
y*= (x1  x2) x3 x1 x3 x2
Inverted dual function:
y * = x1x2  x3
y * x1 x3 x2

23. Transformation Rules for SSBDDs
BOOLEAN ALGEBRA
Exchange of nodes: y = x1 x2
Commutative law:
y = x1  x2= x2  x1
Idempotent law:
Node passing: y
y = x1  x1  x2 = = x1  x2 = x2 x1

24. = Properties of SSBDDs y Boolean function: y = x1x2  x3 (x4  x5x6)#1 #0 x3 x4 x5 x6
Exchange of nodes: y = x1 x2 y x1 #1 x3 x5 #0 x2 x4 x6

25. = Properties of SSBDDs y y Boolean function: y = x1x2  x3 (x4  x5x6)#1 #0 x3 x4 x5 x6
Exchange of subgraphs: y G1 G2 y G2 G1 = x3 y x4 #1 #0 x1 x2 x5 x6

26. Transformation Rules for SSBDDs
BOOLEAN ALGEBRA
Node passing:
Absorption law: y y
y = x1  x1x2 = x1 x1 x1 = x1 x2 x1 x2
Distributive law: y =
y = x1x2  x1x3= = x1(x2  x3) x1 x2 x3

27. Transformation of SSBDDs to BDDsy
x11
x21 x1 y x2
x12
x31 x4
x13
x22
x32 x1 y x2
x12 x3 x4
x13
x22
x32
SSBDD:
x12
x31 x4
x13
x22
x32 x1 y x2 x4 x3
Optimized BDD: x1 y x2 x4 x3
BDD:

28. Transformation Rules for SSBDDs
BOOLEAN ALGEBRA
Superposition: y z x1 x2 x3 = y x2 x3 x1 y z = x1 x2 x3
Assotiative law:
y = x1  (x2  x3) = = (x1  x2)  x3

29. Properties of SSBDDs Graph related properties: SSBDD is planar asyclic
traceable (Hamiltonian path)
for every internal node there exists a 1-path and 0-path
homogenous 1 y
x11
x21 1
x12
x31 1 x4 1
x13
x22
x32 1

30. BDDs for Flip-Flops q c q’ Elementary BDDs c q’ q q c q’ D Flip-Flop J
JK Flip-Flop c q’ S R J q C K S C q R c q’ U
RS Flip-Flop
U - unknown value

31. Mapping Between Circuit and SSBDD
From circuit to set of SSBDDs
Fan-out stems
FFR D C
FFR
SSBDD2
SSBDD4 Y1
FFR
SSBDD3 A
FFR
SSBDD1
FFR B
SSBDD5 Y2 C E a b c Y

32. Advantages of SSBDDs
Linear complexity: a circuit is represented as a system of SSBDDs, where each fanout-free region (FFR) is representred by a separate SSBDD
One-to-one correspondence between the nodes in SSBDDs and signal paths in the circuit
This allows easily to extend the logic simulation with SSBDDs to simulation of faults on signal paths

33. Shared SSBDDs - S3BDD
Extension of superposition procedure beyond the fan-out nodes of the circuit
Merging several functions in the same graphs by introducing multiple roots
Superpositioning of FFRs
Node of SSBDD  signal path up to fan-out stem
Input of SSBDD  circuit down to primary inputs

34. S3BDDs and Fault Collapsing
& 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 14 11 7 19 15 12 17 3 4 17 16 20 18 2 5 1 15 12 10 13 18 9 8 21 6 10 16 13
Fault collapsing:
From 84 faults to 36 faults
For SSBDD: 50 faults

35. Each node represents different paths (path segments) in the circuit
Shared SSBDDs
& 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Each node represents different paths (path segments) in the circuit
SSSBDD for 19
Node
Path 14
(3) 11
(4) 7
7-19 (4) 15
(3) 12
(4) 3
(5) 4
(5) 14 11 7 19 15 12 17 3 4

36. Synthesis of S3BDD for a Circuit
Superposition of BDDs: G1 X 1 3 Y1
Given circuit C17 3 X 2 1 Y1
Each node in the SSMIBDD represents a signal path in the circuit
Testing a node in SSMIBDD means testing a signal path in the circuit Y1 X 1 3 2 4

37. Synthesis of S3BDD for a Circuit
Given circuit C17
Superposition of BDDs: G4 X 5 2 Y2 3 Y1 X 1 3 2 4 Y2 5
Two-output circuit is represented by a single SSBDD with shared subgraphs

38. Sequentional S3BDDs T2 T3 3 2 T1 9 T2 T3 26 9 14 4 1 8 T1 3 2 7 9 10
10 nodes,
20 stuck-at faults,
2,5 times less 3 2 T1 9 T2 T3 26 9 14 4 1 8 1 T1 3 2 7 9 10 15
25 nodes,
50 stuck-at faults 1 12 T2 22 25 8
& 13 11 16 26 T3 4 5 6 14 17 18 19 20 21 23 24 9
GAIN:
2,5 times
in logic simulation,
2,5 2 = 6,25 times
in fault simulation

39. Structured Interpretation of S3BDDs1 T1 3 2 7 9 10 15 3 2 T1 9
S3BDD represents two subcircuits G
Nodes
Signal paths L
GT1 3
3 – 15 – T1 3 2
2 – 9 – 10 – 15 – T1 5 T1
T1 – 7 – 9 – 10 – 15 – T1 6
Each node in the S3BDD represents a signal path in the circuit

40. Structured Interpretation of S3BDDsG
Nodes
Signal paths L
GT2 8
8 – 12 – 25 – T2 4
G26
T2
T2 – 5 – 21 – 23 – 26 5 9
9 – 11 – 18 – 20 – 21 – 23 – 26 7 14
14 – 17 – 18 – 20 – 21 – 23 – 26
4 – 19 – 20 – 21 – 23 – 26 6 T3
T3 – 6 – 14 – 16 – 19 – 20 – 21 – 23 – 26 1
1 – 8 – 13 – 14 – 16 – 19 – 20 – 21 – 23 – 26 10

41. BDDs and Complexity
Optimization (by ordering of nodes): BDDs for a 2-level AND-OR circuit
BDD optimization:
We start synthesis:
from the most repeated variable
2n nodes
22n - 2 nodes

42. BDDs and Complexity
BDDs for an 8-bit data selector

43. BDDs and Complexity q c q’ Elementary BDDs c q’ q q c q’ D Flip-Flop J
JK Flip-Flop c q’ S R J q C K S C q R c q’ U
RS Flip-Flop
U - unknown value
BDD optimization:
We start synthesis:
from the most important variable, or
from the most repeated variable