1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Review for the Final Exam CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff The FINAL exam is scheduled for Thursday Dec 17 @ 2:15 – 4:15 PM It will be in this room.

4. http://www.registrar.iastate.edu/students/exams/fallexams

5. The exam will cover: Chapter 1 to Chapter 6, and Sections 7.1-7.2 Emphasis will be on Chapter 5, 6, and 7 The exam will be open book and open notes (you can bring up to 5 pages of handwritten notes) plus your textbook. Final Exam Format

6. The exam will be out of 130 points You need 95 points to get an A It will be great if you can score more than 100 points. ▪ but you can’t roll over your extra points 

7. Topics for the Final Exam K-maps for 2, 3, and 4 variables Multiplexers (circuits and function) Synthesis of logic functions using multiplexers Shannon’s Expansion Theorem 1’s complement and 2’s complement representation Addition and subtraction of binary numbers Circuits for adding and subtracting Serial adder Latches (circuits, behavior, timing diagrams) Flip-Flops (circuits, behavior, timing diagrams) Counters Registers Synchronous Sequential Circuits

8. FSMs Moore Machine Mealy Machines State diagrams, state tables, state-assigned tables State minimization Designing a counter Arbiter Circuits Reverse engineering a circuit ASM Charts Register Machines Bus structure and Simple Processors Assembly Language for the Simple Processor Something from Star Wars Topics for the Final Exam

9. How to Study for the Final Exam Form a study group Go over the slides for this class Go over the homeworks again Go over the problems at the end of Ch 5 & 6 Exercise Get some sleep

10. Administrative Stuff Please check your grades on BlackBoard Let me know if something is wrong or missing

11. Sample Problems

12. ASM Charts Given an ASM chart draw the corresponding FSM

13. Cz1=  Reset Bz0=  Az0=  w0= w1= w1= w0= w0= w1= [ Figure 6.3 from the textbook ] [ Figure 6.82 from the textbook ]

15. ASM Charts Given an FSM draw the corresponding ASM Chart

16. [ Figure 6.83 from the textbook ][ Figure 6.23 from the textbook ]

18. Circuit Implementation of FSMs Implement this state-assigned Table using JK flip-flips

20. [ Figure 6.94 from the textbook ] Excitation table with JK flip-flops Circuit Implementation of FSMs Implement this state-assigned Table using JK flip-flips

22. Register Machines: What does this program do? How many balls are left in each register at the end of the program? Register 1 Register 2 Register 3 STEPINSTRUCTIONREGISTERGO TO STEP[BRANCH TO STEP] 1.Deb312 2.Deb234 3.Inc32 4.End

23. Register Machines: Move the contents of register 2 to register 3 Register 1 Register 2 Register 3 STEPINSTRUCTIONREGISTERGO TO STEP[BRANCH TO STEP] 1.Deb312 2.Deb234 3.Inc32 4.End

25. Register 1 Register 2 Register 3 STEPINSTRUCTIONREGISTERGO TO STEP[BRANCH TO STEP] 1.Deb312 2.Deb223 3.Deb146 4.Inc35 5.Inc23 6.Deb278 7.Inc16 8.End Register Machines: What does this program do? How many balls are left in each register at the end of the program?

26. Register Machines: Copy the contents of register 1 to register 3 using register 2 as a temporary storage Register 1 Register 2 Register 3 STEPINSTRUCTIONREGISTERGO TO STEP[BRANCH TO STEP] 1.Deb312 2.Deb223 3.Deb146 4.Inc35 5.Inc23 6.Deb278 7.Inc16 8.End

28. [ Figure 6.75 from the textbook ] What does this circuit do?

29. Find the flip-flops Outputs of the flip-flops = present state variables Inputs of the flip-flops determine the next state variables Determine the logical expressions for the outputs Given this info it is easy to do the state-assigned table Next do the state table Finally, draw the state diagram. Approach

30. Goal Given a circuit diagram for a synchronous sequential circuit, the goal is to figure out the FSM Figure out the present state variables, the next state variables, the state-assigned table, the state table, and finally the state diagram. In other words, the goal is to reverse engineer the circuit.

31. [ Figure 6.75 from the textbook ] What does this circuit do?

32. Find the flip-flops Outputs of the flip-flops = present state variables Inputs of the flip-flops determine the next state variables Determine the logical expressions for the outputs Given this info it is easy to do the state-assigned table Next do the state table Finally, draw the state diagram. Approach

33. [ Figure 6.75 from the textbook ] Where are the inputs?

34. [ Figure 6.75 from the textbook ] Where are the inputs? There is only one input

35. [ Figure 6.75 from the textbook ] Where are the outputs?

36. [ Figure 6.75 from the textbook ] Where are the outputs? There is only one output

37. Where kind of machine is this? Moore or Mealy? output input

38. Moore: because the output does not depend directly on the primary input output input

39. Where are the memory elements?

41. Where are the outputs of the flip-flops?

43. These are the present-state variables

44. Where are the inputs of the flip-flops?

46. These are the next-state variables

47. What are their logic expressions?

48. Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2

49. Where is the output, again?

51. What is its logic expression?

52. z = y 1 y 2

53. This is what we have to work with now (we don’t need the circuit anymore) z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2

54. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00 01 10 11

55. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00 01 10 11

56. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 000 01 0 100 111

57. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 000 01 0 100 111

58. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 000 10 010 00 100 10 110 11

59. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 000 10 010 00 100 10 110 11

60. Let’s derive the state-assigned table z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1

61. We don’t need the logic expressions anymore z = y 1 y 2 Y 1 = wy 1 + wy 2 Y 2 = wy 1 + wy 2 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1

62. We don’t need the logic expressions anymore Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1

63. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z State-assigned table State table

64. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z State-assigned table State table

65. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z A B C D State-assigned table State table

66. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z A B C D State-assigned table State table

67. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z AA BA CA DA State-assigned table State table

68. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z AA BA CA DA State-assigned table State table

69. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z AAB BAC CAD DAD State-assigned table State table

70. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z AAB BAC CAD DAD State-assigned table State table

71. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 Let’s derive the state table Present Next state Output state w=0w=1 z AAB BAC CAD DAD The output is the same in both tables State-assigned table State table

72. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 The two tables for the initial circuit Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 [ Figure 6.76 from the textbook ] State-assigned table State table

73. Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 00000 10 01001 00 10001 0 1100 1 We don’t need the state-assigned table anymore Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 [ Figure 6.76 from the textbook ] State-assigned table State table

74. We don’t need the state-assigned table anymore Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 State table

75. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1

76. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 B / 0 C / 0 D / 1 Because this is a Moore machine the output is tied to the state

77. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 B / 0 C / 0 D / 1 All transitions when the input w is equal to 1

78. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 B / 0 C / 0 D / 1 w=1 All transitions when the input w is equal to 1

79. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 B / 0 C / 0 D / 1 w=1 All transitions when the input w is equal to 0

80. Let’s Draw the State Diagram Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1

81. We are done! Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram State table

82. Almost done. What does this FSM do? Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram State table

83. Almost done. What does this FSM do? Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 State table A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram It sets the output z to 1 when three consecutive 1’s occur on the input w. In other words, it is a sequence detector for the input pattern 111.

84. Another Example (with JK flip-flops)

85. [ Figure 6.77 from the textbook ] What does this circuit do? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

86. Find the flip-flops Outputs of the flip-flops = present state variables Inputs of the flip-flops determine the next state variables Determine the logical expressions for the outputs Given this info it is easy to do the state-assigned table Next do the state table Finally, draw the state diagram. Approach

87. [ Figure 6.77 from the textbook ] Where are the inputs and outputs? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

88. Where are the inputs and outputs? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1 output input

89. What kind of machine is this? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1 output input

90. Where are the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

91. Where are the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

92. Where are the outputs of the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

93. Where are the outputs of the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

94. These are the next-state variables J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

95. Where are the inputs of the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

96. Where are the inputs of the flip-flops? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

97. What are their logic expressions? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

98. What are their logic expressions? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2

99. What is the logic expression of the output? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1 output

100. What is the logic expression of the output? J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1 output z = y 1 y 2

101. This is what we have to work with now (we don’t need the circuit anymore) z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2

102. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00 01 10 11

103. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00 01 10 11

104. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 000 010 100 111

105. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 000 010 100 111

106. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 0001110 0101110 1001100 1101101

107. Let’s derive the excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 0001110 0101110 1001100 1101101

108. The excitation table z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00010100110 0110110 10010100100 11010110101 [ Figure 6.78 from the textbook ]

109. We don’t need the logic expressions anymore z = y 1 y 2 J 1 = w K 2 = w J 2 = w y 1 K 1 = w + y 2 Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00010100110 0110110 10010100100 11010110101 [ Figure 6.78 from the textbook ]

110. We don’t need the logic expressions anymore Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00010100110 0110110 10010100100 11010110101 [ Figure 6.78 from the textbook ]

111. Let’s derive the state table State table Excitation table Present Next state Output state w=0w=1 z

112. Let’s derive the state table State table Excitation table Present Next state Output state w=0w=1 z A B C D This step is easy (map 2-bit numbers to 4 letters)

113. Let’s derive the state table State table Excitation table Present Next state Output state w=0w=1 z A0 B0 C0 D1 This step is easy too (the outputs are the same in both tables)

114. Let’s derive the state table State table Excitation table Present Next state Output state w=0w=1 z A0 B0 C0 D1 How should we do this? ?

115. [ Figure 5.16a from the textbook ] JK Flip-Flop Refresher D = JQ + KQ

116. [ Figure 5.16 from the textbook ] JK Flip-Flop Refresher JQ Q K 0 1 Qt1+  Qt  0 (b) Truth table(c) Graphical symbol J 0 0 0 1 1 1 Qt  1 K D Q Q Q Q J Clock (a) Circuit K

117. Let’s derive the state table State table Excitation table Present Next state Output state w=0w=1 z A0 B0 C0 D1 How should we do this? ?

118. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1

119. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1

120. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A Note that A = 00

121. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A ?

122. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A

123. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A

124. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A

125. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A = 1 = 0

126. Let’s derive the state table Present Next state Output state w=0w=1 z A0 B0 C0 D1 A C =0 Note that C = 10

127. The two tables for the initial circuit State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 Excitation table

128. The state diagram State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram

129. The state diagram State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram Thus, this FSM is identical to the one in the previous example, even though the circuit uses JK flip-flops.

130. Yet Another Example (with mixed flip-flops)

131. [ Figure 6.79 from the textbook ] What does this circuit do?

132. Find the flip-flops Outputs of the flip-flops = present state variables Inputs of the flip-flops determine the next state variables Determine the logical expressions for the outputs Given this info it is easy to do the state-assigned table Next do the state table Finally, draw the state diagram. Approach

133. [ Figure 6.79 from the textbook ] What are the logic expressions?

135. D 1 = w (y 1 + y 2 ) T 2 = w y 2 + w y 1 y 2 z = y 1 y 2

136. The Excitation Table Excitation table Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 000001010 010010100 101001010 111001011 D 1 = w (y 1 + y 2 ) T 2 = w y 2 + w y 1 y 2 z = y 1 y 2

137. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table

138. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D This step is easy (map 2-bit numbers to 4 letters)

139. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D This step is easy too (the outputs are the same in both tables) 0 0 0 1

140. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D What should we do here? 0 0 0 1 ?

141. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D What should we do here? 0 0 0 1 ?

142. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1

143. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1

144. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1

145. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 0

146. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 0

147. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 0

148. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 0 A Note that A = 00

149. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D What should we do here? 0 0 0 1 ? A

150. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 A

151. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 A

152. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 A

153. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 1 A

154. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 1 A

155. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 1 A

156. Present Next state Output state w=0w=1 z Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table A B C D 0 0 0 1 1 D Note that D = 11 A

157. Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 Let’s derive the state table

158. Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1 The two tables for the initial circuit State table Excitation table [ Figure 6.80 from the textbook ] [ Figure 6.75b from the textbook ]

159. The state diagram State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram

160. The state diagram State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 A / 0 w=0 B / 0 C / 0 D / 1 w=0 w=1 State diagram Thus, this FSM is identical to the ones in the previous examples, even though the circuit uses JK flip-flops.

162. State Minimization

163. Present Next state Output state w=0w=1 z ABC1 BDF1 CFE0 DBG1 EFC0 FED0 GFG0 State Table for This Example [ Figure 6.51 from the textbook ]

164. A B C D E F G State Diagram (just the states)

165. A B C D E F G State Diagram (transitions when w=0)

166. A B C D E F G State Diagram (transitions when w=1)

167. A B C D E F G z=1 z=0 Outputs

168. A B C D E F G z=1 z=0 Partition #1 (All states in the same partition)

169. A B C D E F G z=1 z=0 Partition #1 (ABCDEFG)

170. A B C D E F G z=1 z=0 Partition #2 (based on outputs) z=1z=0

171. A B C D E F G z=1 z=0 Partition #2 (ABD)(CEFG) z=1z=0

172. A B C D E F G z=1 z=0 Partition #3.1 (Examine the 0-successors of ABD)

173. A B C D E F G z=1 z=0 Partition #3.1 (Examine the 1-successors of ABD)

174. A B C D E F G z=1 z=0 Partition #3.2 (Examine the 0-successors of CEFG)

175. A B C D E F G z=1 z=0 Partition #3.2 (Examine the 1-successors of CEFG)

176. A B C D E F G z=1 z=0 Partition #3.2 (Examine the 1-successors of CEFG) This needs to be in a new block

177. A B C D E F G z=1 z=0 Partition #3 (ABD)(CEG)(F)

178. A B C D E F G z=1 z=0 Partition #3 (ABD)(CEG)(F)

179. A B C D E F G z=1 z=0 Partition #4.1 (Examine the 0-successors of ABD)

180. A B C D E F G z=1 z=0 Partition #4.1 (Examine the 1-successors of ABD)

181. A B C D E F G z=1 z=0 Partition #4.1 (Examine the 1-successors of ABD) This needs to be in a new block

182. A B C D E F G z=1 z=0 Partition #4 (AD)(B)(CEG)(F)

183. A B C D E F G z=1 z=0 Partition #4 (AD)(B)(CEG)(F)

184. A B C D E F G z=1 z=0 Partition #5.1 (Examine the 0-successors of AD)

185. A B C D E F G z=1 z=0 Partition #5.1 (Examine the 1-successors of AD)

186. A B C D E F G z=1 z=0 Partition #5.2 (Examine the 0-successors of B)

187. A B C D E F G z=1 z=0 Partition #5.2 (Examine the 1-successors of B)

188. A B C D E F G z=1 z=0 Partition #5.3 (Examine the 0-successors of CEG)

189. A B C D E F G z=1 z=0 Partition #5.3 (Examine the 1-successors of CEG)

190. A B C D E F G z=1 z=0 Partition #5.4 (Examine the 0-successors of F)

191. A B C D E F G z=1 z=0 Partition #5.4 (Examine the 1-successors of F)

192. Partition #5 (AD)(B)(CEG)(F) A B C D E F G z=1 z=0

193. Partition #4 (AD)(B)(CEG)(F) A B C D E F G z=1 z=0

194. Partition #5 (This is the same as #4 so we can stop here) A B C D E F G z=1 z=0

195. Present Nextstate Output state w=0w=1 z ABC1 BAF1 CFC0 FCA0 [ Figure 6.52 from the textbook ] Minimized state table

196. Multiplexers

197. 4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3

198. Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

199. 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer [ Figure 4.3 from the textbook ]

200. Implementation of a logic function [ Figure 4.7 from the textbook ] w 3 w 3 f w 1 0 w 2 1 (a) Modified truth table (b) Circuit 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3

201. 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

202. f w 1 w 2 (a) Truth table (b) Circuit 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9 from the textbook ]

203. Gated D Latch

204. [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch

205. Edge-Triggered D Flip-Flops

206. (a) Circuit D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a from the textbook ] Master-Slave D Flip-Flop

207. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

208. [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch

209. Constructing a D Flip-Flop

211. (with one less NOT gate)

212. Constructing a D Flip-Flop (with one less NOT gate)

213. T Flip-Flop

214. [ Figure 5.15a from the textbook ] T Flip-Flop

215. [ Figure 5.15a from the textbook ] T Flip-Flop Positive-edge-triggered D Flip-Flop

216. [ Figure 5.15a from the textbook ] T Flip-Flop What is this?

217. Q Q T D

218. Q Q T D += ?

219. T 0 1 D Q Q Clock T Flip-Flop

220. What is this? += ?

221. T D Q Q Clock T Flip-Flop

222. JK Flip-Flop

223. [ Figure 5.16a from the textbook ] JK Flip-Flop D = JQ + KQ

224. [ Figure 5.16 from the textbook ] JK Flip-Flop JQ Q K 0 1 Qt1+  Qt  0 (b) Truth table(c) Graphical symbol J 0 0 0 1 1 1 Qt  1 K D Q Q Q Q J Clock (a) Circuit K

225. JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop

226. Registers

227. Register (Definition) An n-bit structure consisting of flip-flops

228. A simple shift register [ Figure 5.17 from the textbook ]

229. Parallel-access shift register [ Figure 5.18 from the textbook ]

230. Counters

231. A three-bit up-counter [ Figure 5.19 from the textbook ]

232. A three-bit up-counter [ Figure 5.19 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count012345670 (b) Timing diagram

233. A three-bit down-counter [ Figure 5.20 from the textbook ]

234. A three-bit down-counter [ Figure 5.20 from the textbook ] T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count076543210 (b) Timing diagram

235. Synchronous Counters

236. A four-bit synchronous up-counter [ Figure 5.21 from the textbook ]

237. Synchronous Counter with D Flip-Flops

238. A four-bit counter with D flip-flops [ Figure 5.23 from the textbook ]

239. Counters with Parallel Load

240. A counter with parallel-load capability [ Figure 5.24 from the textbook ]

241. A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]

242. What does this circuit do? [ Figure 5.25a from the textbook ]

243. Designing The Control Circuit

244. A Simple Processor [ Figure 7.9 from the textbook ]

245. The function register and decoders [ Figure 7.11 from the textbook ]

246. A part of the control circuit for the processor Reset Up-counter Clear w 0 En y 0 w 1 y 1 y 2 y 3 1 T 1 T 2 T 3 2-to-4 decoder Q 1 Q 0 Clock T 0 [ Figure 7.10 from the textbook ]

247. Control signals asserted in each time step [ Table 7.2 from the textbook ] T1T1 T2T2 T3T3 (Load): I 0 Extern R in = X Done (Move): I 1 R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = 1 G out R in = X Done

248. Operations performed by this processor [ Table 7.1 from the textbook ] OperationFunction Performed Load Rx, Data Rx  Data Move Rx, Ry Rx  [Ry] Add Rx, Ry Rx  [Rx] + [Ry] Sub Rx, Ry Rx  [Rx] - [Ry]

249. Operations performed by this processor [ Table 7.1 from the textbook ] OperationFunction Performed Load Rx, Data Rx  Data Move Rx, Ry Rx  [Ry] Add Rx, Ry Rx  [Rx] + [Ry] Sub Rx, Ry Rx  [Rx] - [Ry] Where Rx and Ry can be one of four possible options: R0, R1, R2, and R3

250. f1f1 f0f0 Function 00Load 01Move 10Add 11Sub Rx 1 Rx 0 Register 00R0 01R1 10R2 11R3 Ry 1 Ry 0 Register 00R0 01R1 10R2 11R3 Operations performed by this processor

251. f1f1 f0f0 Function 00Load 01Move 10Add 11Sub Rx 1 Rx 0 Register 00R0 01R1 10R2 11R3 Ry 1 Ry 0 Register 00R0 01R1 10R2 11R3  Move R3, R0 0 1 1 1 0 0 Operations performed by this processor

252. f1f1 f0f0 Function 00Load 01Move 10Add 11Sub Rx 1 Rx 0 Register 00R0 01R1 10R2 11R3 Ry 1 Ry 0 Register 00R0 01R1 10R2 11R3  Add R1, R3 1 0 0 1 1 1 Operations performed by this processor

253. f1f1 f0f0 Function 00Load 01Move 10Add 11Sub Rx 1 Rx 0 Register 00R0 01R1 10R2 11R3 Ry 1 Ry 0 Register 00R0 01R1 10R2 11R3  Sub R0, R2 1 1 0 0 1 0 Operations performed by this processor

254. f1f1 f0f0 Function 00Load 01Move 10Add 11Sub Rx 1 Rx 0 Register 00R0 01R1 10R2 11R3 Ry 1 Ry 0 Register 00R0 01R1 10R2 11R3  Load R2, Data 0 0 1 0 x x Operations performed by this processor

255. Similar Encoding is Used by Modern Chips [http://en.wikipedia.org/wiki/Instruction_set]

256. Sample Assembly Language Program For This Processor Move R3, R0 Add R1, R3 Sub R0, R2 Load R2, Data

257. Machine Language vs Assembly Language Move R3, R0 Add R1, R3 Sub R0, R2 Load R2, Data R3  [R0] R1  [R1] + [R3] R0  [R0] – [R2] R2  Data 011100 100111 110010 001000 Machine LanguageAssembly Language Meaning / Interpretation

258. Machine Language vs Assembly Language Move R3, R0 Add R1, R3 Sub R0, R2 Load R2, Data R3  [R0] R1  [R1] + [R3] R0  [R0] – [R2] R2  Data 011100 100111 110010 001000 Machine LanguageAssembly Language Meaning / Interpretation

259. Machine Language vs Assembly Language Move R3, R0 Add R1, R3 Sub R0, R2 Load R2, Data R3  [R0] R1  [R1] + [R3] R0  [R0] – [R2] R2  Data 011100 100111 110010 001000 Machine LanguageAssembly Language Meaning / Interpretation For short, each line can be expresses as a hexadecimal number

260. Machine Language vs Assembly Language Move R3, R0 Add R1, R3 Sub R0, R2 Load R2, Data R3  [R0] R1  [R1] + [R3] R0  [R0] – [R2] R2  Data 1C 27 32 08 Machine LanguageAssembly Language Meaning / Interpretation

261. Questions?

262. THE END