1. Processor Structure and Function Chapter8:

2. CPU Structure  CPU must:  Fetch instructions –Read instruction from memory  Interpret instructions –Instruction decoded to determine the action  Fetch data –Execution Instruction may require reading data from memory/ I/O module  Process data –Execution Instruction may require performing some arithmetic/ logical operation on data  Write data –Result from execution may require writing data to memory/ I/O module

3. CPU With Systems Bus  Major component of processor:  ALU  CU  Registers (internal memory)  ALU does the actual computation/processing of data  CU controls the data and instruction movement into and out of the processor. Also controls ALU operation

4. CPU Internal Structure

5. Registers  CPU must have some working space (temporary storage) called registers  Number and function vary between processor designs  One of the major design decisions  Top level of memory hierarchy

6. User Visible Registers  Enable machine/assembly language programmer to minimize main memory reference by optimizing use of register  Category :  General Purpose  Data  Address  Condition Codes

7. General Purpose Registers (1)  May be true general purpose  May be restricted (eg. For floating point / stack operation)  May be used for data or addressing  Data – only hold data  Accumulator  Addressing  Segment pointer  Index register  Stack pointer

8. General Purpose Registers (2)  Make them general purpose —Increase flexibility and programmer options —Increase instruction size & complexity  Make them specialized —Smaller (faster) instructions —Less flexibility

9. How Many GP Registers?  Between 8 - 32  Fewer = more memory references  More does not reduce memory references and takes up processor real estate  See also RISC

10. How big?  Large enough to hold full address  Large enough to hold full word  Often possible to combine two data registers —C programming —double int a; —long int a;

11. Condition Code Registers  Sets of individual bits —e.g. result of last operation was zero  Can be read (implicitly) by programs —e.g. Jump if zero  Can not (usually) be set by programs

12. Control & Status Registers  Variety of processor registers that are employed to control operation of processor  4 registers are necessary to instruction execution: 1.Program Counter 2.Instruction Decoding Register 3.Memory Address Register 4.Memory Buffer Register  Revision: what do these all do?

13. Program Status Word  Processor design include register or set of registers and known as PSW, that contain information  contains condition codes + other status info  Common field or flags include:  Sign of last result  Zero  Carry  Equal  Overflow  Interrupt enable/disable  Supervisor

14. Supervisor Mode  Intel ring zero  Kernel mode  Allows privileged instructions to execute  Used by operating system  Not available to user programs

15. Other Registers  May have registers pointing to: —Process control blocks (see O/S) —Interrupt Vectors (see O/S)  N.B. CPU design and operating system design are closely linked

16. Example Register Organizations

17. Instruction Cycle  Revision  Stallings Chapter 3

18. Indirect Cycle  May require memory access to fetch operands  Indirect addressing requires more memory accesses  Can be thought of as additional instruction subcycle

19. Instruction Cycle with Indirect

20. Instruction Cycle State Diagram

21. Data Flow (Instruction Fetch)  Depends on CPU design  In general:  Fetch –PC contains address of next instruction –Address moved to MAR –Address placed on address bus –Control unit requests memory read –Result placed on data bus, copied to MBR, then to IR –Meanwhile PC incremented by 1

22. Data Flow (Fetch Diagram)

23. Data Flow (Data Fetch)  IR is examined  If indirect addressing, indirect cycle is performed —Right most N bits of MBR transferred to MAR —Control unit requests memory read —Result (address of operand) moved to MBR

24. Data Flow (Indirect Diagram)

25. Data Flow (Execute)  May take many forms  Depends on instruction being executed  May include —Memory read/write —Input/Output —Register transfers —ALU operations

26. Data Flow (Interrupt)  Simple  Predictable  Current PC saved to allow resumption after interrupt  Contents of PC copied to MBR  Special memory location (e.g. stack pointer) loaded to MAR  MBR written to memory  PC loaded with address of interrupt handling routine  Next instruction (first of interrupt handler) can be fetched

27. Data Flow (Interrupt Diagram)

28. Prefetch  Fetch accessing main memory  Execution usually does not access main memory  Can fetch next instruction during execution of current instruction  Called instruction prefetch

29. Improved Performance  But not doubled: —Fetch usually shorter than execution –Prefetch more than one instruction? —Any jump or branch means that prefetched instructions are not the required instructions  Add more stages to improve performance

30. Computer Performance(1)  Understanding computer performance:  Algorithm – determines number of operations executed  Programming language, compiler, architecture – determines number of machine instructions executed per operation  Processor and memory system – determine how fast instruction are executed  I/O system (incl. OS) – determines how fast I/O operations are executed

31. Computer Performance(2)

32. Performance – Let’s look at this…

33. Computer Performance(3)

34. Response Time and Throughput  Response Time  how long it takes to do a task  Throughput  total of work done per unit time  How are Response Time and Throughput affected by  replacing the processor with a faster version?  adding more processors?

35. CPU Clocking  Operation of computer hardware governed by constant-rate of clock

36. Execution Time(1)  The execution time is defined in terms of:  Elapsed Time  counts everything  a useful number, but often not good for comparison purposes  CPU Time  does not count I/O or time spent running other programs

37. Execution Time(2)

38. Basic Definition of Performance(1)  For some program running on machine X, (Performance) x = 1/(execution time) x When X is n times faster than Y machine (Performance) x / (Performance) y = n Problem: Machine A runs a program in 20s Machine B runs the same program in 25s How to improve performance - everything else being equal we can either:  reduce the number of required cycle for a program, or  reduce the clock cycle time (clock rate)

39. Basic Definition of Performance(2)  Hardware Designer must often trade off clock rate against clock count  Can we assume: # of cycle = # of instructions?  multiplication takes more time than addition  floating-point operations take longer than integer  accessing memory takes more time than registers

40. CPU Time – proportional to instruction count(1)

41. CPU Time – proportional to instruction count(2) Any additional instruction you execute takes time. CPU Time: proportional to clock period - how can architects reduce clock period? Instruction’s execution time in “number of cycles” - short clock period => short execution time. What ultimately limits an architect’s ability to reduce the clock periods?

42. CPU Time – Example(1)

43. CPU Time – Example(2) Solution:

44. Aspects of CPU Performance(1)

45. Aspects of CPU Performance(2)

46. Performance Equation

47. Amdahl’s Law(1)

48. Amdahl’s Law(2)

49. Enhancement by Multiple CPUs

50. Experimental Example

51. Points to remember…..