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Interfacing External Memory Rajiv Nandivada. High Level Schematic Clock cycle of 10-20 ns (Depending on its use). 3.3 V CMOS SRAM (128 x 8 bit). Uses.

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Presentation on theme: "Interfacing External Memory Rajiv Nandivada. High Level Schematic Clock cycle of 10-20 ns (Depending on its use). 3.3 V CMOS SRAM (128 x 8 bit). Uses."— Presentation transcript:

1 Interfacing External Memory Rajiv Nandivada

2 High Level Schematic Clock cycle of 10-20 ns (Depending on its use). 3.3 V CMOS SRAM (128 x 8 bit). Uses multiplexed address and data bus to reduce the number of port pins. The lower address bits are held in latch while the data is transferred.

3 Functional Block Diagram of SRAM Single 3.3 V supply. Lower power consumption via chip deselect. Available in 32 pin Plastic SOJ, and 32 pin Type II TSOP packages.

4 Truth Table

5 Pin Configuration SOJ and TSOP Top View SOJ: Small Outline J Leads TSOP: Thin Small Outline Package

6 Characteristics SymbolRatingValueUnit V DD Supply voltage relative to GND -0.5 to +4.6 V V IN,V OUT Terminal voltage relative to GND -0.5 to V DD +0.5 V TATATATACommercial Operating Temp Industrial 0 to +70 -40 to +85 0C0C0C0C0C0C0C0C T BIAS Temperature under bias -55 to +125 0C0C0C0C T STG Storage Temperature -55 to +125 0C0C0C0C PTPTPTPT Power Dissipation 1.25W I OUT DC Output Current 50mA

7 Timing Diagrams Read cycle: Write cycle:

8 Major Manufacturers of SRAM Alliance, Alliance, Brilliance Brilliance Crosslink Crosslink Cypress Semiconductor Cypress Semiconductor Dense-PAC Micro Dense-PAC Micro Etron Technology Etron Technology Eureka Eureka Hitachi Hitachi IBM IBM IDT IDT Mitsubishi Mitsubishi NEC NEC Samsung Samsung Seiko Epson Seiko Epson Sharp Sharp Sony Sony Toshiba Toshiba

9 Electrically Erasable Programmable Read-only Memory (EEPROM)

10 Erasable Programmable Read-only Memory (EPROM)

11 Flash Memory

12 I 2 C(Inter IC) Bus SDA: Serial Data Line SCL: Serial Clock Line

13 Packaging  SOJ or Small Outline J-lead  TSOP or Thin Standard Outline Package  DIP or Dual Inline Package  ZIP or Zigzag Inline Package PLCC or Plastic Leaded Chip Carrier PLCC or Plastic Leaded Chip Carrier

14 Packaging Contd..   SOJ or Small Outline J-lead   TSOP or Thin Standard Outline Package   DIP or Dual Inline Package   ZIP or Zigzag Inline Package   PLCC or Plastic Leaded Chip Carrier

15 Pricing Depends on The type of package it comes in (DIP, SOJ, TSOP) The type of package it comes in (DIP, SOJ, TSOP) The speed of the memory. The speed of the memory. The market value. The market value. The vendor (Digikey, Jameco) The vendor (Digikey, Jameco) Storage capacity( 128K X 8, 256K X 8) Storage capacity( 128K X 8, 256K X 8) The type of memory (Flash, EEPROM) The type of memory (Flash, EEPROM)

16 References www.cygnal.com www.cygnal.com www.digikey.com www.digikey.com www.srams.co.uk www.srams.co.uk www.jameco.com www.jameco.com www.atmel.com www.atmel.com www.xicor.com www.xicor.com


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