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© 2005, it - instituto de telecomunicações. Todos os direitos reservados. Tools and Methods to Assist Analog IC Designers Nuno Horta, PhD Head of Integrated.

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Presentation on theme: "© 2005, it - instituto de telecomunicações. Todos os direitos reservados. Tools and Methods to Assist Analog IC Designers Nuno Horta, PhD Head of Integrated."— Presentation transcript:

1 © 2005, it - instituto de telecomunicações. Todos os direitos reservados. Tools and Methods to Assist Analog IC Designers Nuno Horta, PhD Head of Integrated Circuits Group Instituto de Telecomunicações Analog IC Design Automation

2 2 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

3 3 MOTIVATION ANALOG IC Design and CAD tools Are available to handle typical design flows Cadence and HSPICE are Schematic and simulation oriented Designers need to apply their expertise for simulation and resizing which is largely crafted by hand Assisted simulation and resizing is considered the most time consuming process Lack of commercial DA tools at both circuit and layout–level synthesis. 3 1 4 5 6 2 January 6, 2016 8:36 PM

4 4 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

5 5 ANALOG IC DA: OVERVIEW (CIRCUIT-LEVEL SYNTHESIS) Tools and Methods Evolution January 6, 2016 8:36 PM

6 6 ANALOG IC DA: OVERVIEW (LAYOUT-LEVEL SYNTHESIS) Tools and Methods Evolution January 6, 2016 8:36 PM

7 7 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

8 8 CASE STUDIES AIDA – Analog IC Design Automation Environment (1 of 3) AIDA results from the integration of GENOM-POF and LAYGEN-II GENOM-POF: Circuit-Level Synthesis Multi-objective Multi-constraint Optimization-based Approach Robust design: Corners validation and Electrical Simulation LAYGEN II: Layout-Level Generation Template-based Approach DRC proved fully automated layout generation January 6, 2016 8:36 PM

9 9 CASE STUDIES AIDA – Analog IC Design Automation Environment (2 of 3) LEVEL of AUTOMATION from circuit to layout DOMAIN and PROBLEM COMPLEXITY circuit synthesis and layout generation optimization problem complexity (CL) – modified NSGA-II Kernel circuit complexity (CL) – SVM models to prune search space optimization problem complexity (LL) – Hierarchical Template Descrip. circuit complexity (LL) – built-in DRC evaluation engine January 6, 2016 8:36 PM

10 10 CASE STUDIES AIDA – Analog IC Design Automation Environment (3 of 3) SOLUTION ROBUSTNESS account to extreme variations (CL) - corners validation parametric module generator (LL) multi-objective multi-constraint optimization kernels (CL, LL) DESIGNER INTERFACE file level (CL) GUI in Java TM (LL) DEGREE of INTEGRATION with Ctools standard Spice like netlists as entry standard GDSII file as output January 6, 2016 8:36 PM

11 11 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

12 12 CS1: Circuit-Level Synthesis - GENOM-POF (1 of 3) Design Specs INPUT to CL Synthesis circuit and testbench description search space definition optimization variable ranges optimization problem definition performance constraints functional constraints objectives single-ended folded cascode amplifier circuit testbench January 6, 2016 8:36 PM

13 13 CS1: Circuit-Level Synthesis - GENOM-POF (2 of 3) Multi-Objective Evolutionary Optimization Kernel Optimization Kernel Modified NSGA-II Phase 1: Typical Optimization Phase 2: Corners Optimization POF (Pareto Optimal Front) Each POF point is a optimal sized circuit (Time [s] = 227 (226 sim)!!) Phase 1 Phase 2 January 6, 2016 8:36 PM

14 14 CS1: Circuit-Level Synthesis - GENOM-POF (3 of 3) Tracking Optimization Process Convergence Measures POF area number of POF elements NSGA-II Parameters Population size Crossover Mutation January 6, 2016 8:36 PM

15 15 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

16 16 CS2: Layout-Level Synthesis - LAYGEN II Design Specs INPUT to LL Synthesis Template description Device Type Relative Placement Device sizes Technology Design Kit (UMC130nm) Design Rules Parametric Module Generator Diff-amp with a current mirror load Template view January 6, 2016 8:36 PM

17 17 CS2: Layout-Level Synthesis - LAYGEN II PLACER Placer Instantiation - Packing (Phase 1) Device Sizes Module Generator for the target Technology Technology Design Kit January 6, 2016 8:36 PM

18 18 CS2: Layout-Level Synthesis - LAYGEN II PLACER Placer Packing (Phase2) Biasing Abutment Overlapped connection between two cells. Saves space, reduces wiring length, possible parasitics reduction. January 6, 2016 8:36 PM

19 19 CS2: Layout-Level Synthesis - LAYGEN II PLACER Placer Packing (Phase3) Minimum distances Guard ring Enhanced Immunity against latchup Minimum convex polygon January 6, 2016 8:36 PM

20 20 CS2: Layout-Level Synthesis - LAYGEN II Router Initialization Template (connectivity, symmetry and sensitivity constraints) Optimization (NSGA II Kernel) Built in checkers ( DRC – Design Rule Checker; SCC – Short Circuit Checker; ERC – Electric Rule Checker ) Phase 1: Global Solution (faster) Phase 2: Detailed Solution (accurate) January 6, 2016 8:36 PM

21 21 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Case Studies Conclusions January 6, 2016 8:36 PM

22 22 CS: LAYGEN II Case Study I: Hierarchical Layout Generation fully-dynamic comparator [Goes et al, 2011] Hierarchical Template Description device sizes PLACER January 6, 2016 8:36 PM

23 23 CS: LAYGEN II Case Study I: Hierarchical Layout Generation PLACER ROUTER fully-dynamic comparator [Goes et al, 2011] handmade layout [Goes et al, 2011] January 6, 2016 8:36 PM

24 24 CS: LAYGEN II Case Study I: Hierarchical Layout Generation fully-dynamic comparator [Goes et al, 2011] DRC and LVS with CALIBRE® Comparator Simulation Schematic (Red) Handmade (Black) LAYGEN II (Green) January 6, 2016 8:36 PM

25 25 CS: GENOM-POF and LAYGEN II Design 1 Design 2 Design 3 single-ended folded cascode amplifier Design 1 Design 2 Design 3 January 6, 2016 8:36 PM Case Study II: From Circuit-Level Specs to GDSII Description

26 26 CS: GENOM-POF and LAYGEN II Case Study II: From Circuit-Level Specs to GDSII Description Design 1 Design 2 Design 3 Design 1Design 2Design 3 single-ended folded cascode amplifier January 6, 2016 8:36 PM

27 27 OUTLINE Motivation Analog IC DA: Overview ICG DA Tools and Methods: Circuit-Level Synthesis: GENOM-POF (N. Lourenço, N. Horta) Layout-Level Synthesis: LAYGEN II (R. Martins, N. Lourenço, N. Horta) Conclusions January 6, 2016 8:36 PM

28 28 AIDA, based on GENOM-POF and LAYGEN II, achieves competitive results with existing SOA solutions in the area of Analog IC Design Automation @ Circuit-Level Multi-objective multi-constrained optimization based on modified NSGA-II optimization kernel High accuracy by implementing an optimization based approach using an electrical simulation as the evaluation engine Robust solution by considering Corners validation @ Layout-Level Fast prototyping based on a template based approach and on built- in DRC, SCC, ERC modules. Robust solution by including simultaneously multi-objective optimization together with final validation with CALIBRE® DRC a main reference in the ICs design intended for fabrication. Future work, mainly, moving to system-level synthesis and deep nanometer technologies. CONCLUSIONS January 6, 2016 8:36 PM

29 29 END January 6, 2016 8:36 PM

30 30 MOTIVATION  Electronic Design Automation  Constraints (**) “Exponential Trends in the IC Industries” - Scotten Jones + - - (*)(*) (**) The Moore's Law New Challenges January 6, 2016 8:36 PM

31 31 ANALOG IC DA: OVERVIEW (CIRCUIT-LEVEL SYNTHESIS) Knowledge-BasedvsOptimization-Based Pros and Cons (+) short execution time (-) difficult to scale (-) design plan too complex (-) low accuracy Pros and Cons (+) high accuracy, scalable, no need for design plan (-) time consumption January 6, 2016 8:36 PM

32 32 ANALOG IC DA: OVERVIEW (LAYOUT-LEVEL SYNTHESIS) Optimization-Based, Template-Based and Procedural Approaches January 6, 2016 8:36 PM

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