1. Chapter 15 Differential Amplifiers and Operational Amplifier Design
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Microelectronic Circuit Design, 3E
McGraw-Hill

2. Microelectronic Circuit Design, 3E
Op Amp Output Stages
Output stage is designed to provide low output resistance and relatively high current drive capability.
Followers: Class-A amplifiers- transistors conduct during full 3600 of signal waveform, conduction angle =3600.
Push-pull: Class-B- each of the two transistors conducts during 1800of signal wavefrom, conduction angle =1800.
Class-AB: Characteristics of Class-A and Class-B are combined, most commonly used as output stage in op amps.
Microelectronic Circuit Design, 3E
McGraw-Hill

3. Source-Follower: Class-A Output Stage
For a source-follower,difference between input and output voltages is fixed and voltage transfer characteristic is as shown. If load resistor is connected to output, total source current:
vMIN = -ISS RL and iS=0, M1cuts off when vI = -ISS RL + VTN.
Microelectronic Circuit Design, 3E
McGraw-Hill

4. Source-Follower: Class-A Output Stage
If output signal is given by:
Efficiency of amplifier is given by:
Low efficiency is due to current ISS that constantly flows between the two supplies.
Microelectronic Circuit Design, 3E
McGraw-Hill

5. Class-B Push-Pull Output Stage
Improve efficiency by operating transistors at zero Q-point current eliminating quiescent power dissipation. NMOS transistor is a source-follower for positive input signals and NMOS transistor is a source-follower for negative input signals.
Since neither transistor conducts when,
output waveform suffers from a dead-zone or crossover distortion.
Microelectronic Circuit Design, 3E
McGraw-Hill

6. Microelectronic Circuit Design, 3E
Class-AB Amplifiers
The required bias voltage can be developed as shown.We assume that bias voltage splits equally between gate-source(or base-drain) terminals.
Currents are given by
Benefits of Class-B amplifier can be maintained without dead zone by biasing transistors into conduction but at a low quiescent current level (<< peak ac current delivered to load). For each transistor, 1800< conduction angle <3600.
Microelectronic Circuit Design, 3E
McGraw-Hill

7. Class-AB Output Stages for Op Amps
Microelectronic Circuit Design, 3E
McGraw-Hill

8. MOS Current Mirrors: DC Analysis
However, VDS1 is not equal to VDS2 and there is slight mismatch between output and reference currents. Mirror ratio is:
MOSFETs M1 and M2 are assumed to have identical VTN, Kn’, l, and W/L ratios.
IREF provides operating bias to mirror.
VDS1 = VGS1= VGS2 =VGS
Microelectronic Circuit Design, 3E
McGraw-Hill

9. MOS Current Mirror (Example)
Problem:Calculate output current for given current mirror.
Given data: IREF = 150 mA, VSS = 10 V, VTN = 1 V, Kn = 250 mA/V2, l = V-1
Analysis: (1+ l VDS1) term is neglected to simplify dc bias calculation.
Actual currents are found to be mismatched by approximately 10%.
Microelectronic Circuit Design, 3E
McGraw-Hill

10. MOS Current Mirrors: Changing Mirror Ratio
Mirror ratio can be changed by modifying W/L ratios of the two transistors forming the mirror.
In given current mirror, Io =5IREF. Again mismatch in VDS causes error in MR.
Microelectronic Circuit Design, 3E
McGraw-Hill

11. Bipolar Current Mirrors: DC Analysis
BJTs Q1 and Q2 are assumed to have identical IS, VA, bFO, and W/L ratios.
Io = IC2, IREF = IC1 + IB1 + IB2
VBE1= VBE2 =VBE
Finite current gain of BJT causes slight mismatch between Io and IREF.
Microelectronic Circuit Design, 3E
McGraw-Hill

12. Current Mirror (Example)
Problem:Calculate and compare mirror ratios for BJT and MOS current mirror.
Given data: IREF = 150 mA, VGS = 2 V, VDS2 = VCE2 = 10 V, l = 0.02 V-1 VA = 50 V, bFO = 100, VSS = 10 V, M1 = M2, Q1 = Q2.
Analysis:
Microelectronic Circuit Design, 3E
McGraw-Hill