1. Wafer Edge Exclusion
Kevin Fisher

2. Outline What is Edge Exclusion? Motivation for reducing edge exclusion
ITRS Roadmap
Problems on the Edge
Example: Copper Deposition

3. What is Edge Exclusion?
Edge of wafer considered unusable for a variety of reasons
Chips entirely on wafer but too close to edge are still invalidated

4. Yield Loss on the Edge Current edge exclusion is 3mm
Reduces usable area of wafer by 2%
300mm wafer: mm2 total area
297mm usable area: mm2
Area loss: 1406 mm2
Athlon 64 die size: 144 mm2

5. Increasing Yield
300mm Pentium 4 Processor wafer (130nm)

6. ITRS on Edge Exclusion Two references in 2003 Yield Enhancement report
Wafer Type
2003
2004
Patterned
2mm
1mm
Unpatterned
3mm

7. Problems on the Edge Chips, cracks, identification notches
Slurry/photoresist residue
Cleaning contaminants
Peeling films

8. Copper Interconnects
Two problems affect edges of wafers with copper metal layers
Barrier, seed layer residue
Copper islands

9. Barrier/Seed Residue

10. Copper Islands

11. One Solution: Wet Processing Chambers
Apply film in liquid-filled chamber
Chemical breaks film’s surface tension