1. REGISTER MANAGMENT TOOL Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 17/05/13 Duration: Two Semesters Final presentation – Part B

2. M ANY TEAMS NEED TO CREATE THEIR OWN REGISTER BLOCKS FOR FPGA SYSTEMS. L EADING TO BUGS Double Effort T HE S OLUTION A R EGISTER M ANAGEMENT T OOL Automatically generates registers according to a required specification using a smart interface!

3. I NSERT YOUR PROJECT ’ S SPECIFICATIONS TO THE GUI A UTOMATICALLY CREATE VHD AND HSID FOR REGISTER BLOCKS ! A UTO R EG – A SMART REGISTER MANAGEMENT TOOL

4. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. T HE S OLUTION – A R EGISTER M ANAGEMENT T OOL Creates unity in the registers VHD files Automatically generates registers according to the required specification. Enables REUSE Saves money and resources

5. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. T HE S OLUTION – A R EGISTER M ANAGEMENT T OOL Creates documentation for the components created Leads to an organized – HSID Alarms in case of incorrect input Manages the registers through the entire project

6. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user.

7. P ROJECT S PECIFICATIONS 1. Writing a GUI interface through which the user will determine a variety of attributes. 4. No special license will be needed to operate the tool, an EXE file will be given to the user. 3. VHDL: VHD files Local Bus Master Simulation Environment 2. Interactivity - The tool will provide feedback for user errors and will provide a summary output. 5. HSID will be generated under IEEE standards (IP-XACT)

8. P ROJECT S TEPS 1. Determine the implementation platform of the user interface and data processing: Excel/MATLAB/C++/C#/JAVA. 2. Full characterization of the tool capabilities. 3. Learning the working environment (Wishbone protocol, advanced VHDL coding, MODELSIM simulation environment). 4. VHDL generic design and simulation. 5. Implementing the GUI (Graphic User Interface) 6. Implementing Automatic VHDL generation. 7. Final MODELSIM and MATLAB Simulations.

9. VHDL I MPLEMENTATION

10. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. G ENERAL D ESCRIPTION Block Local Bus Chip data I/O Register access Register Block

11. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. VHDL T OP A RCHITECTURE Block_A_reg_top Function_2 Function_3 Function_1 Block A Reg_status_1 Wishbone Master Reg_enable_2 func_err_3 resetclk

12. o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. WB Slave Reg1 Reg2 Reg3 Reg4 Priority Encoder reg_chosen 4 WB Master Functional Block Data from chosen register Inputs from block Outputs to block Block_A_reg_top R EG B LOCK A RCHITECTURE

13. G ENERIC I MPLEMENTATION

15. VHDL S IMULATION

16. S IMULATION E NVIRONMENT Macro Scripts

17. S IMULATION E NVIRONMENT Compilation Simulation Waveforms Test Bench Macro Scripts

18. S IMULATION E NVIRONMENT Macro Scripts Compilation Simulation Waveforms Test Bench Procedure called serially many times Comparison to expected values Reporting results to output file Waveforms Results Output File Simulation outputs Simulation input

19. T EST P LAN - O VERVIEW Testing small modules separately gen_reg.vhd: Read Write Read/Write Clear On Read Const. wbs_reg.vhd Read transactions (single/burst) Write transactions (single/burst) encoder_generic.vhd Then, testing the entire design Gen_block.vhd

20. T EST P LAN – C ASES Testing Regular Activity Various generic values for address width Various values for data Read/Write single/burst wishbone cycles for suitable registers Testing system boundaries Testing system generics

21. S YNTHESIS

22. S YNTHESIS R ESULTS A synthesis demonstration was ran, using Quartus II 12.0sp2, using the following test case: 32 registers, with 8-bit data width, with device EP4CGX50DF27C6 Compilation and Synthesis finished successfully. Summaries: Maximum Frequencies: Slow 1.2V 85C model – 1199MHz Slow 1.2V 0C model – 1328MHz

23. N ETLISTS

24. G RAPHICAL U SER I NTERFACE

25. Easy to use user experience Feedback is provided in real time Data is filled automatically if possible Easy project view and management Data and Address can be represented in both Hexadecimal and Decimal formats R EQUIREMENTS FROM GUI

26. O PENING S CREEN – PROJECT SETTINGS Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Browser for finding the requested directory

27. O PENING S CREEN – PROJECT SETTINGS Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Continue to next screen

28. 2 ND S CREEN – E DIT B LOCK SETTINGS Settings made for the specific block Specify a name Provide a description (optional) Opens text editor

29. 2 ND S CREEN – E DIT B LOCK SETTINGS Settings made for the specific block Specify a name Provide a description (optional) Specify an initial address Specify number of registers choose reset polarity back to project settings delete current block Continue to next screen Navigation tree view

30. 3 RD SCREEN – E DIT REGISTER SETTINGS Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value Navigation tree view Back to block settings delete current register

31. 3 RD SCREEN – E DIT REGISTER SETTINGS Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value

32. T OP MENUS File menu Help menu Create a new project Open an existing project Save project as Save current project Close current project Exit AutoReg About AutoReg Open user guide Generate menu Report for errors Generate VHDL files

33. T REE V IEW “ Top View ” of the entire project Automatically sorted by the absolute address Allows easy navigation between all the screens and components Addresses and names are filled automatically Navigation is blocked when errors or missing data is found in the current window

34. E RRORS D ISPLAY AutoReg notifies the user and prevents access to some contents in the project whenever: Data isn’t legal/valid/ complete Addresses/bits are overlapping Before Deleting an object Easy to use user experience Feedback is provided in real time

35. O UTPUTS

36. E RROR R EPORT

37. HSID

38. XML – ACCORDING TO IP-XACT STANDARD

39. VHD files and reports are created in two sub- folders: VHD FILES

40. DEMO

41. S UGGESTIONS FOR A LATER PROJECT 1.An option to create a wide register (more than one address). 2.Support other protocols (not wishbone only) 3.Support more register types 4.Add a possibility to mix between the bits of the same register when it comes to access manners. 5.Support boards and not just on FPGA 6.Search and filter possibilities 7.Copy-Paste possibilities

42. S UGGESTIONS FOR A LATER PROJECT 8. Creating a database with options to import and export 9. An option to duplicate, add or delete a register using a right-click option from the tree view. 10. Unifying the edit_block figure and the edit_reg figure to prevent window from “jumping” 11. Under the help menu, add a keyboard map for all keyboard shortcuts of the GUI. Link : AutoReg Gui - other features.docxAutoReg Gui - other features.docx

43. T HE E ND