1. ECE 331 – Digital System Design Multi-bit Adder Circuits, Adder/Subtractor Circuit, and Multiplier Circuit (Lecture #12)

2. ECE 331 - Digital System Design2 Implementations of Multi-bit Adders: 1. Ripple Carry Adder 2. Carry Lookahead Adder

3. ECE 331 - Digital System Design3 Ripple Carry Adder Multi-bit Adder Circuits

4. ECE 331 - Digital System Design4 FA x n –1 c n c n1” y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position Ripple Carry Adder Carry ripples from one stage to the next Carry-in Carry-out

5. ECE 331 - Digital System Design5 Ripple Carry Adder in VHDL 22 2

6. ECE 331 - Digital System Design6 Ripple Carry Adder in VHDL library ieee; use ieee.std_logic_1164.all; use work.pack.all; ENTITY add3bit IS PORT (a : IN std_logic_vector(2 downto 0); b : IN std_logic_vector(2 downto 0); cin : IN std_logic; s : OUT std_logic_vector(2 downto 0); cout : OUT std_logic); END add3bit;

7. ECE 331 - Digital System Design7 Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cin1, cin2: std_logic; BEGIN fa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 ); fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 ); fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout ); END struct;

8. ECE 331 - Digital System Design8 Ripple Carry Adder in VHDL CinCout ARCHITECTURE struct OF add3bit IS SIGNAL cin1, cin2: std_logic; BEGIN fa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 ); fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 ); fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout ); END struct;

9. ECE 331 - Digital System Design9 Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cy : std_logic_vector (3 downto 0); BEGIN fa0: fa PORT MAP(a(0),b(0),cy(0), s(0), cy(1)); fa1: fa PORT MAP(a(1),b(1),cy(1), s(1), cy(2)); fa2: fa PORT MAP(a(2),b(2),cy(2), s(2), cy(3)); END struct; CinCout

10. ECE 331 - Digital System Design10 Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cy : std_logic_vector (3 downto 0); BEGIN Adders: FOR i IN 0 TO 2 GENERATE myfa:fa PORT MAP(a(i),b(i),cy(i),s(i),cy(i+1)); END GENERATE; cout <= cy(3); cy(0) <= cin; END struct;

11. ECE 331 - Digital System Design11 The Ripple Carry Adder is slow! Why? How can the speed of the adder be increased?

12. ECE 331 - Digital System Design12 Increasing the speed of the Adder Method A: Include all inputs and outputs in the design  Inputs = X i, Y i, C in,i ; Outputs = S i, C out,i 1-bit3 inputs2 outputs 2-bit5 inputs3 outputs 4-bit9 inputs5 outputs n-bit2n+1 inputsn+1 outputs  Large number of operands, but only 2 logic levels Increase in speed Increase in area required decrease propagation delay increase # of logic gates Use Truth Table and K-Map to derive logic functions

13. ECE 331 - Digital System Design13 Increasing the speed of the Adder Method B: Manipulate the Boolean Expressions

14. ECE 331 - Digital System Design14 Carry Lookahead Adder Multi-bit Adder Circuits

15. ECE 331 - Digital System Design15 Carry Lookahead Adder 1001 0011+ 1 Carry Generate 1101 Carry End 11 Carry Propagate 0111 1010 0001 00 10 10 11 X Y

16. ECE 331 - Digital System Design16 Carry Lookahead Adder Carry Generate  G i = X i. Y i  Always generates a carry if G i evaluates to true. Carry Propagate  P i = X i + Y i  Generates a carry if P i evaluates to true AND there was a Carry-In. Propagates the Carry-In if true.

17. ECE 331 - Digital System Design17

18. ECE 331 - Digital System Design18 Carry Lookahead Adder The Carry Generate (G i ) and Carry Propagate (P i ) can be created directly from the inputs. no ripple delay only 1 gate delay

19. ECE 331 - Digital System Design19 Carry Lookahead Adder C out,i is a function of G i and P i C out,i = (X i.Y i ) + ( (X i + Y i ).(C in,i ) )  This is the C out of the Full Adder C out,i = (G i ) + ( (P i ).(C in,i ) )  where C in,i = C out,i-1

20. ECE 331 - Digital System Design20 Carry Lookahead Adder For the LSB,  C out,i = (G 0 ) + ( (P 0 ).(C in,0 ) )  no ripple delay

21. ECE 331 - Digital System Design21 Carry Lookahead Adder For LSB+1:  C out,1 = (G 1 ) + ( (P 1 ). C in,1 )  C out,1 = (G 1 ) + ( (P 1 ). C out,0 )  C out,1 = (G 1 ) + ( (P 1 ). (G 0 + P 0.C in,0 ) )  C out,1 = G 1 + P 1.G 0 + P 1.P 0.C in,0 All G and P terms derived directly from associated inputs No ripple delay

22. ECE 331 - Digital System Design22 Carry Lookahead Adder For LSB+2:  C out,2 = (G 2 ) + ( (P 2 ). C in,2 )  C out,2 = (G 2 ) + ( (P 2 ). C out,1 )  C out,2 = (G 2 ) + ( (P 2 ). (G 1 + P 1.C in,1 ) )  C out,2 = (G 2 ) + ( (P 2 ). (G 1 + P 1.C out,0 ) )  C out,2 = G 2 + P 2.G 1 + P 2.P 1.C out,0 Similar for LSB+3, LSB+4, etc. Must be expanded in terms of G 0, P 0, and C in,0

23. ECE 331 - Digital System Design23 x 1 y 1 g 1 p 1 s 1 x 0 y 0 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

24. ECE 331 - Digital System Design24 Carry Lookahead Adder Sum: S i is a function of X i, Y i, and C in,i  S i = X i xor Y i xor C in,i  S i = X i xor Y i xor C out,i-1 Carry: C out,i derived from G i and P i  G i and P i are functions of the inputs Carries do not ripple from one stage to the next  Delay ~ log 2 (n)  Area required ~ (n)*(log 2 (n)) Greater than area required for RCA

25. ECE 331 - Digital System Design25 Carry Lookahead Adder 74LS283: 4-bit Binary Adder with Fast Carry

26. ECE 331 - Digital System Design26 Hierarchical Design: Building a bigger Adder Multi-bit Adder Circuits

27. ECE 331 - Digital System Design27 Block x 3124– c 32 c 24 y 3124– s 3124– x 158– c 16 y 158– s 8– c 8 x 70– y 70– s 70– c 0 3 Block 1 0 Hierarchical Design Carry Lookahead Adder Ripple carry (between blocks)

28. ECE 331 - Digital System Design28 Adder / Subtractor using Two's Complement

29. ECE 331 - Digital System Design29 Adder / Subtractor using Two’s Complement Could build separate binary adder and subtractor  Not common Use Two’s Complement integer representation  Addition uses binary adder  Subtraction uses binary adder with the Two’s Complement representation for the subtrahend Issues  Cannot directly convert the most negative n-bit binary number to Two’s complement representation  Must detect overflow

30. ECE 331 - Digital System Design30 Adder / Subtractor

31. ECE 331 - Digital System Design31 Detecting Overflow Compare sign of operands with sign of result  Overflow occurs if operands have same sign and result has different sign Addition of two positive #s results in negative # Addition of two negative #s results in positive # Logic function(s) for overflow (for a 4-bit Adder)  Overflow = X 3.Y 3.S 3 ' + X 3 '.Y 3 '.S 3  Overflow = C 3 xor C 4 = C 3 '.C 4 + C 3.C 4 '

32. ECE 331 - Digital System Design32 Multiplier Circuit

33. ECE 331 - Digital System Design33 Multiplier Circuit Multiplication requires two basic operations:  Addition  Logical Shift A binary multiplier circuit can be designed hierarchically using  Full Adders  AND gates

34. ECE 331 - Digital System Design34 Binary Multiplication  1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 Multiplicand M Multiplier Q Product P (11) (14) (154) + 1 0 1 0 1 0 0 + 0 1 0 1 0 1 1 1 0 + Partial product 0 Partial product 1 Partial product 2 4 bits 8 bits # of bits in P = # of bits in M + # of bits in Q

35. ECE 331 - Digital System Design35 Binary Multiplication M (Multiplicand) = m 3 m 2 m 1 m 0 Q (Multiplier) = q 3 q 2 q 1 q 0 PP0 = m 3.q 0 m 2.q 0 m 1.q 0 m 0.q 0 0pp0 3 pp0 2 pp0 1 pp0 0 +m 3.q 1 m 2.q 1 m 1.q 1 m 0.q 1 0 PP1 = pp1 4 pp1 3 pp1 2 pp1 1 pp1 0 partial product

36. ECE 331 - Digital System Design36 Multiplier Circuit PP1 PP2

37. ECE 331 - Digital System Design37 Multiplier Circuit Bit of PPi