1. Lecture 5 Computer Hardware

3. von Neumann Architecture

4. Secondary Storage - The Disc Drive

5. The Very Simple Computer

6. Half Adder

7. Full Adder

8. N-Bit Adder

9. Ripple-Carry Adder

10. S-R Latch and D-Type Flip Flop

11. Register Transfer

12. The Fetch - Execute Cycle

13. Running the VSC

20. Fetch-Execute Cycle Timing Diagram

21. Control Unit Executing OpCodes LDA en - load ACC enable - moves value in LAT1 into ACC STA en - store ACC enable - moves value in ACC into MEM[MAR] ADD en - ADD enable CMP en - CMP (1's complement) enable - takes the bitwise inverse of LAT1 BNN en - if(ACC7 = 0) then PC = IR SHLen - shift-left enable SHR en - shift-right enable HLT en - halts the fetch-execute cycle by setting Control Unit IR

22. Arithmetic Logic Unit

23. Programming the VSC addr label instruction addr machine code. 0 LDA A 00000 00000100 1 ADD B 00001 01000101 2 STO C 00010 00100110 3 HLT 00011 11111111 4 A 24 00100 00011000 5 B 30 00101 00011110 6 C 0 00110 00000000

24. Types of Multiprocessors SISD - Single Instruction - Single Data SIMD - Single Instruction - Multiple Data MISD - Multiple Instruction - Single Data MIMD - Multiple Instruction- Multiple Data