1. Designing Sequential Logic Circuits Ilam university

2. Sequential Logic

3. Naming Conventions  In our text:  a latch is level sensitive  a register is edge-triggered  There are many different naming conventions  For instance, many books call edge- triggered elements flip-flops  This leads to confusion however

4. Latch versus Register  Latch stores data when clock is high D Clk Q D Q  Register stores data when clock rises Clk D D QQ

5. Latches

6. Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

7. Characterizing Timing Register Latch

8. Storage Mechanisms

9. Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

10. Meta-Stability Gain should be larger than 1 in the transition region

11. Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

12. Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

13. Mux-Based Latch

14. NMOS onlyNon-overlapping clocks

15. Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

16. Master-Slave Register Multiplexer-based latch pair

17. Clk-Q Delay

18. Setup Time

19. Reduced Clock Load Master-Slave Register

20. Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

21. Maximum Clock Frequency

23. Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

24. Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset

25. Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building memory cell

26. Sizing Issues Output voltage dependence on transistor width Transient response

27. Storage Mechanisms D CLK Q Dynamic (charge-based) Static

28. Making a Dynamic Latch Pseudo-Static

29. More Precise Setup Time

30. Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

31. Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

32. Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

33. Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

34. Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

35. Setup/Hold Time Illustrations Hold-1 case 0

36. Setup/Hold Time Illustrations Hold-1 case 0

37. Setup/Hold Time Illustrations Hold-1 case 0

38. Setup/Hold Time Illustrations Hold-1 case 0

39. Setup/Hold Time Illustrations Hold-1 case 0